CoreIR based mapping tool for CGRA
stanfordaha / cgramapper Goto Github PK
View Code? Open in Web Editor NEWCoreIR based mapping tool for CGRA
License: BSD 3-Clause "New" or "Revised" License
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Requires to be installed
Currently running the mapper requires coreir to be installed on the system.
I suggest allowing a default location of where coreir exists (for example, search in CGRAMapper/../coreir). This would allow a user to not install coreir onto their system.
Mapper doesn't handle ashr properly
See
CGRAMapper/src/definitions/cgralib_def.h
Line 182 in b9ab907
I'm going over every operator that's mapped to the CGRA and it seems like currently the mapper doesn't care about whether the operator is signed or not. As a result, given the suggestions #68, the bitstream generated directly from alu_op and signed is completely wrong. That is, using the op name in the prefix of each instance combined with alu_op_debug can produce correct harris bitstream, whereas using opcode + signed cannot.
In this case, most operators are still functional with either singed or unsigned inputs, but ashrs behavior is different. The current implementation will fail when the input is larger than 0x8000.
I will also talked to @jeffsetter to see which operator used in Halide behaves differently with signed or unsigned inputs.
ERROR: NYI using mutliple memories
> ./bin/cgra-mapper demosaic_design_top.json demosaic_mapped.json
Running Pass: rungenerators
In Run Generators
ERROR: NYI using mutliple memories
cgra-mapper(+0x3db77)[0x55b8758d5b77]
cgra-mapper(+0x4d0a7)[0x55b8758e50a7]
libcoreir.so(_ZNKSt8functionIFvPN6CoreIR7ContextESt3mapINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPNS0_5ValueESt4lessIS9_ESaISt4pairIKS9_SB_EEEPNS0_9ModuleDefEEEclES2_SI_SK_+0x76)[0x7fa974fbc2d8]
libcoreir.so(_ZN6CoreIR19GeneratorDefFromFun15createModuleDefEPNS_9ModuleDefESt3mapINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEPNS_5ValueESt4lessIS9_ESaISt4pairIKS9_SB_EEE+0x93)[0x7fa974fba46d]
ibcoreir.so(_ZN6CoreIR6Module12runGeneratorEv+0x184)[0x7fa97506012a]
libcoreir.so(_ZN6CoreIR6Passes13RunGenerators12runOnContextEPNS_7ContextE+0x229)[0x7fa97519df77]
libcoreir.so(_ZN6CoreIR11PassManager14runContextPassEPNS_4PassE+0x35)[0x7fa97501e259]
libcoreir.so(_ZN6CoreIR11PassManager7runPassEPNS_4PassE+0xfe)[0x7fa97501edea]
libcoreir.so(_ZN6CoreIR11PassManager3runESt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS7_EES9_+0x571)[0x7fa97501fc4d]
libcoreir.so(_ZN6CoreIR7Context9runPassesESt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS7_EES9_+0x91)[0x7fa9750996f9]
bin/cgra-mapper(+0x4aca5)[0x55b8758e2ca5]
/lib/x86_64-linux-gnu/libc.so.6(__libc_start_main+0xe7)[0x7fa974055b97]
bin/cgra-mapper(+0x3c7ca)[0x55b8758d47ca]
demosaic_design_top.json
{"top":"global.DesignTop",
"namespaces":{
"global":{
"modules":{
"DesignTop":{
"type":["Record",[
["in",["Record",[["arg_1",["Array",1,["Array",1,["Array",16,"BitIn"]]]]]]],
["out",["Array",1,["Array",1,["Array",3,["Array",16,"Bit"]]]]]
]],
"instances":{
"add_628_630_631":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_637_639_640":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_644_646_647":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_647_649_650":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_650_652_653":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_665_667_668":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_668_670_671":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_671_673_674":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_692_694_695":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_695_697_698":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_698_700_701":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_706_708_709":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_715_717_718":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_725_727_728":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_732_740_741":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_734_736_737":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_745_747_748":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_752_760_761":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_754_756_757":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_765_767_768":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_772_780_781":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_774_776_777":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_demosaic_2_x___scan_dim_0-1_619":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_demosaic_2_x___scan_dim_0-1_659":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_demosaic_2_x___scan_dim_0-1_684":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_demosaic_2_y___scan_dim_1-1_623":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_demosaic_2_y___scan_dim_1-1_675":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"add_demosaic_2_y___scan_dim_1-1_688":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"and_619_620_621":{
"genref":"coreir.and",
"genargs":{"width":["Int",16]}
},
"and_623_620_624":{
"genref":"coreir.and",
"genargs":{"width":["Int",16]}
},
"and_659_660_661":{
"genref":"coreir.and",
"genargs":{"width":["Int",16]}
},
"and_675_660_676":{
"genref":"coreir.and",
"genargs":{"width":["Int",16]}
},
"and_684_685_686":{
"genref":"coreir.and",
"genargs":{"width":["Int",16]}
},
"and_688_685_689":{
"genref":"coreir.and",
"genargs":{"width":["Int",16]}
},
"ashr_631_632_633":{
"genref":"coreir.ashr",
"genargs":{"width":["Int",16]}
},
"ashr_640_632_641":{
"genref":"coreir.ashr",
"genargs":{"width":["Int",16]}
},
"ashr_653_654_655":{
"genref":"coreir.ashr",
"genargs":{"width":["Int",16]}
},
"ashr_674_678_679":{
"genref":"coreir.ashr",
"genargs":{"width":["Int",16]}
},
"ashr_701_702_703":{
"genref":"coreir.ashr",
"genargs":{"width":["Int",16]}
},
"ashr_709_710_711":{
"genref":"coreir.ashr",
"genargs":{"width":["Int",16]}
},
"ashr_718_710_719":{
"genref":"coreir.ashr",
"genargs":{"width":["Int",16]}
},
"ashr_728_729_730":{
"genref":"coreir.ashr",
"genargs":{"width":["Int",16]}
},
"ashr_737_729_738":{
"genref":"coreir.ashr",
"genargs":{"width":["Int",16]}
},
"ashr_741_729_742":{
"genref":"coreir.ashr",
"genargs":{"width":["Int",16]}
},
"ashr_748_749_750":{
"genref":"coreir.ashr",
"genargs":{"width":["Int",16]}
},
"ashr_757_749_758":{
"genref":"coreir.ashr",
"genargs":{"width":["Int",16]}
},
"ashr_761_749_762":{
"genref":"coreir.ashr",
"genargs":{"width":["Int",16]}
},
"ashr_768_769_770":{
"genref":"coreir.ashr",
"genargs":{"width":["Int",16]}
},
"ashr_777_769_778":{
"genref":"coreir.ashr",
"genargs":{"width":["Int",16]}
},
"ashr_781_769_782":{
"genref":"coreir.ashr",
"genargs":{"width":["Int",16]}
},
"const-1_-1":{
"genref":"coreir.const",
"genargs":{"width":["Int",16]},
"modargs":{"value":[["BitVector",16],"16'hffff"]}
},
"const-1_-1$1":{
"genref":"coreir.const",
"genargs":{"width":["Int",16]},
"modargs":{"value":[["BitVector",16],"16'hffff"]}
},
"const-1_-1$2":{
"genref":"coreir.const",
"genargs":{"width":["Int",16]},
"modargs":{"value":[["BitVector",16],"16'hffff"]}
},
"const-1_-1$3":{
"genref":"coreir.const",
"genargs":{"width":["Int",16]},
"modargs":{"value":[["BitVector",16],"16'hffff"]}
},
"const-1_-1$4":{
"genref":"coreir.const",
"genargs":{"width":["Int",16]},
"modargs":{"value":[["BitVector",16],"16'hffff"]}
},
"const-1_-1$5":{
"genref":"coreir.const",
"genargs":{"width":["Int",16]},
"modargs":{"value":[["BitVector",16],"16'hffff"]}
},
"const0_0":{
"genref":"coreir.const",
"genargs":{"width":["Int",16]},
"modargs":{"value":[["BitVector",16],"16'h0000"]}
},
"const0_0$1":{
"genref":"coreir.const",
"genargs":{"width":["Int",16]},
"modargs":{"value":[["BitVector",16],"16'h0000"]}
},
"const0_0$2":{
"genref":"coreir.const",
"genargs":{"width":["Int",16]},
"modargs":{"value":[["BitVector",16],"16'h0000"]}
},
"const0_0$3":{
"genref":"coreir.const",
"genargs":{"width":["Int",16]},
"modargs":{"value":[["BitVector",16],"16'h0000"]}
},
"const0_0$4":{
"genref":"coreir.const",
"genargs":{"width":["Int",16]},
"modargs":{"value":[["BitVector",16],"16'h0000"]}
},
"const0_0$5":{
"genref":"coreir.const",
"genargs":{"width":["Int",16]},
"modargs":{"value":[["BitVector",16],"16'h0000"]}
},
"const1__620$3":{
"genref":"coreir.const",
"genargs":{"width":["Int",16]},
"modargs":{"value":[["BitVector",16],"16'h0001"]}
},
"const1__620$4":{
"genref":"coreir.const",
"genargs":{"width":["Int",16]},
"modargs":{"value":[["BitVector",16],"16'h0001"]}
},
"const1__632":{
"genref":"coreir.const",
"genargs":{"width":["Int",16]},
"modargs":{"value":[["BitVector",16],"16'h0001"]}
},
"const1__632$1":{
"genref":"coreir.const",
"genargs":{"width":["Int",16]},
"modargs":{"value":[["BitVector",16],"16'h0001"]}
},
"const1__660":{
"genref":"coreir.const",
"genargs":{"width":["Int",16]},
"modargs":{"value":[["BitVector",16],"16'h0001"]}
},
"const1__660$1":{
"genref":"coreir.const",
"genargs":{"width":["Int",16]},
"modargs":{"value":[["BitVector",16],"16'h0001"]}
},
"const1__685":{
"genref":"coreir.const",
"genargs":{"width":["Int",16]},
"modargs":{"value":[["BitVector",16],"16'h0001"]}
},
"const1__685$1":{
"genref":"coreir.const",
"genargs":{"width":["Int",16]},
"modargs":{"value":[["BitVector",16],"16'h0001"]}
},
"const1__710":{
"genref":"coreir.const",
"genargs":{"width":["Int",16]},
"modargs":{"value":[["BitVector",16],"16'h0001"]}
},
"const1__710$1":{
"genref":"coreir.const",
"genargs":{"width":["Int",16]},
"modargs":{"value":[["BitVector",16],"16'h0001"]}
},
"const1__729":{
"genref":"coreir.const",
"genargs":{"width":["Int",16]},
"modargs":{"value":[["BitVector",16],"16'h0001"]}
},
"const1__729$1":{
"genref":"coreir.const",
"genargs":{"width":["Int",16]},
"modargs":{"value":[["BitVector",16],"16'h0001"]}
},
"const1__729$2":{
"genref":"coreir.const",
"genargs":{"width":["Int",16]},
"modargs":{"value":[["BitVector",16],"16'h0001"]}
},
"const1__749":{
"genref":"coreir.const",
"genargs":{"width":["Int",16]},
"modargs":{"value":[["BitVector",16],"16'h0001"]}
},
"const1__749$1":{
"genref":"coreir.const",
"genargs":{"width":["Int",16]},
"modargs":{"value":[["BitVector",16],"16'h0001"]}
},
"const1__749$2":{
"genref":"coreir.const",
"genargs":{"width":["Int",16]},
"modargs":{"value":[["BitVector",16],"16'h0001"]}
},
"const1__769":{
"genref":"coreir.const",
"genargs":{"width":["Int",16]},
"modargs":{"value":[["BitVector",16],"16'h0001"]}
},
"const1__769$1":{
"genref":"coreir.const",
"genargs":{"width":["Int",16]},
"modargs":{"value":[["BitVector",16],"16'h0001"]}
},
"const1__769$2":{
"genref":"coreir.const",
"genargs":{"width":["Int",16]},
"modargs":{"value":[["BitVector",16],"16'h0001"]}
},
"const2__654":{
"genref":"coreir.const",
"genargs":{"width":["Int",16]},
"modargs":{"value":[["BitVector",16],"16'h0002"]}
},
"const2__678":{
"genref":"coreir.const",
"genargs":{"width":["Int",16]},
"modargs":{"value":[["BitVector",16],"16'h0002"]}
},
"const2__702":{
"genref":"coreir.const",
"genargs":{"width":["Int",16]},
"modargs":{"value":[["BitVector",16],"16'h0002"]}
},
"count__demosaic_2_x___scan_dim_0":{
"genref":"commonlib.counter",
"genargs":{"inc":["Int",1], "max":["Int",1441], "min":["Int",0], "width":["Int",16]}
},
"count__demosaic_2_x___scan_dim_0_reset":{
"modref":"corebit.const",
"modargs":{"value":["Bool",false]}
},
"count__demosaic_2_x___scan_dim_0_wen":{
"modref":"corebit.const",
"modargs":{"value":["Bool",true]}
},
"count__demosaic_2_y___scan_dim_1":{
"genref":"commonlib.counter",
"genargs":{"inc":["Int",1], "max":["Int",961], "min":["Int",0], "width":["Int",16]}
},
"count__demosaic_2_y___scan_dim_1_reset":{
"modref":"corebit.const",
"modargs":{"value":["Bool",false]}
},
"count__demosaic_2_y___scan_dim_1_wen":{
"modref":"corebit.const",
"modargs":{"value":["Bool",true]}
},
"eq_6210_622":{
"genref":"coreir.eq",
"genargs":{"width":["Int",16]}
},
"eq_6240_625":{
"genref":"coreir.eq",
"genargs":{"width":["Int",16]}
},
"eq_6610_662":{
"genref":"coreir.eq",
"genargs":{"width":["Int",16]}
},
"eq_6760_677":{
"genref":"coreir.eq",
"genargs":{"width":["Int",16]}
},
"eq_6860_687":{
"genref":"coreir.eq",
"genargs":{"width":["Int",16]}
},
"eq_6890_690":{
"genref":"coreir.eq",
"genargs":{"width":["Int",16]}
},
"lb_demosaic_2_stencil_update_stream":{
"genref":"commonlib.linebuffer",
"genargs":{"has_valid":["Bool",false], "image_type":["CoreIRType",["Array",961,["Array",1441,["Array",3,["Array",16,"Bit"]]]]], "input_type":["CoreIRType",["Array",1,["Array",1,["Array",3,["Array",16,"BitIn"]]]]], "is_last_lb":["Bool",true], "output_type":["CoreIRType",["Array",2,["Array",2,["Array",3,["Array",16,"Bit"]]]]]}
},
"lb_demosaic_2_stencil_update_stream_wen":{
"modref":"corebit.const",
"modargs":{"value":["Bool",true]}
},
"lb_padded_2_stencil_update_stream":{
"genref":"commonlib.linebuffer",
"genargs":{"has_valid":["Bool",false], "image_type":["CoreIRType",["Array",963,["Array",1443,["Array",16,"Bit"]]]], "input_type":["CoreIRType",["Array",1,["Array",1,["Array",16,"BitIn"]]]], "is_last_lb":["Bool",true], "output_type":["CoreIRType",["Array",3,["Array",3,["Array",16,"Bit"]]]]}
},
"lb_padded_2_stencil_update_stream_wen":{
"modref":"corebit.const",
"modargs":{"value":["Bool",true]}
},
"mux_622_626_634":{
"genref":"coreir.mux",
"genargs":{"width":["Int",16]}
},
"mux_622_642_656":{
"genref":"coreir.mux",
"genargs":{"width":["Int",16]}
},
"mux_625_635_657":{
"genref":"coreir.mux",
"genargs":{"width":["Int",16]}
},
"mux_662_663_680":{
"genref":"coreir.mux",
"genargs":{"width":["Int",16]}
},
"mux_662_680_663":{
"genref":"coreir.mux",
"genargs":{"width":["Int",16]}
},
"mux_677_681_682":{
"genref":"coreir.mux",
"genargs":{"width":["Int",16]}
},
"mux_687_704_712":{
"genref":"coreir.mux",
"genargs":{"width":["Int",16]}
},
"mux_687_720_721":{
"genref":"coreir.mux",
"genargs":{"width":["Int",16]}
},
"mux_690_713_722":{
"genref":"coreir.mux",
"genargs":{"width":["Int",16]}
}
},
"connections":[
["lb_padded_2_stencil_update_stream.out.1.0","add_628_630_631.in0"],
["lb_padded_2_stencil_update_stream.out.1.2","add_628_630_631.in1"],
["ashr_631_632_633.in0","add_628_630_631.out"],
["lb_padded_2_stencil_update_stream.out.0.1","add_637_639_640.in0"],
["lb_padded_2_stencil_update_stream.out.2.1","add_637_639_640.in1"],
["ashr_640_632_641.in0","add_637_639_640.out"],
["lb_padded_2_stencil_update_stream.out.0.0","add_644_646_647.in0"],
["lb_padded_2_stencil_update_stream.out.0.2","add_644_646_647.in1"],
["add_647_649_650.in0","add_644_646_647.out"],
["lb_padded_2_stencil_update_stream.out.2.0","add_647_649_650.in1"],
["add_650_652_653.in0","add_647_649_650.out"],
["lb_padded_2_stencil_update_stream.out.2.2","add_650_652_653.in1"],
["ashr_653_654_655.in0","add_650_652_653.out"],
["lb_padded_2_stencil_update_stream.out.1.0","add_665_667_668.in0"],
["lb_padded_2_stencil_update_stream.out.1.2","add_665_667_668.in1"],
["add_668_670_671.in0","add_665_667_668.out"],
["lb_padded_2_stencil_update_stream.out.0.1","add_668_670_671.in1"],
["add_671_673_674.in0","add_668_670_671.out"],
["lb_padded_2_stencil_update_stream.out.2.1","add_671_673_674.in1"],
["ashr_674_678_679.in0","add_671_673_674.out"],
["lb_padded_2_stencil_update_stream.out.0.0","add_692_694_695.in0"],
["lb_padded_2_stencil_update_stream.out.0.2","add_692_694_695.in1"],
["add_695_697_698.in0","add_692_694_695.out"],
["lb_padded_2_stencil_update_stream.out.2.0","add_695_697_698.in1"],
["add_698_700_701.in0","add_695_697_698.out"],
["lb_padded_2_stencil_update_stream.out.2.2","add_698_700_701.in1"],
["ashr_701_702_703.in0","add_698_700_701.out"],
["lb_padded_2_stencil_update_stream.out.0.1","add_706_708_709.in0"],
["lb_padded_2_stencil_update_stream.out.2.1","add_706_708_709.in1"],
["ashr_709_710_711.in0","add_706_708_709.out"],
["lb_padded_2_stencil_update_stream.out.1.0","add_715_717_718.in0"],
["lb_padded_2_stencil_update_stream.out.1.2","add_715_717_718.in1"],
["ashr_718_710_719.in0","add_715_717_718.out"],
["lb_demosaic_2_stencil_update_stream.out.0.0.0","add_725_727_728.in0"],
["lb_demosaic_2_stencil_update_stream.out.0.1.0","add_725_727_728.in1"],
["ashr_728_729_730.in0","add_725_727_728.out"],
["ashr_728_729_730.out","add_732_740_741.in0"],
["ashr_737_729_738.out","add_732_740_741.in1"],
["ashr_741_729_742.in0","add_732_740_741.out"],
["lb_demosaic_2_stencil_update_stream.out.1.0.0","add_734_736_737.in0"],
["lb_demosaic_2_stencil_update_stream.out.1.1.0","add_734_736_737.in1"],
["ashr_737_729_738.in0","add_734_736_737.out"],
["lb_demosaic_2_stencil_update_stream.out.0.0.1","add_745_747_748.in0"],
["lb_demosaic_2_stencil_update_stream.out.0.1.1","add_745_747_748.in1"],
["ashr_748_749_750.in0","add_745_747_748.out"],
["ashr_748_749_750.out","add_752_760_761.in0"],
["ashr_757_749_758.out","add_752_760_761.in1"],
["ashr_761_749_762.in0","add_752_760_761.out"],
["lb_demosaic_2_stencil_update_stream.out.1.0.1","add_754_756_757.in0"],
["lb_demosaic_2_stencil_update_stream.out.1.1.1","add_754_756_757.in1"],
["ashr_757_749_758.in0","add_754_756_757.out"],
["lb_demosaic_2_stencil_update_stream.out.0.0.2","add_765_767_768.in0"],
["lb_demosaic_2_stencil_update_stream.out.0.1.2","add_765_767_768.in1"],
["ashr_768_769_770.in0","add_765_767_768.out"],
["ashr_768_769_770.out","add_772_780_781.in0"],
["ashr_777_769_778.out","add_772_780_781.in1"],
["ashr_781_769_782.in0","add_772_780_781.out"],
["lb_demosaic_2_stencil_update_stream.out.1.0.2","add_774_776_777.in0"],
["lb_demosaic_2_stencil_update_stream.out.1.1.2","add_774_776_777.in1"],
["ashr_777_769_778.in0","add_774_776_777.out"],
["count__demosaic_2_x___scan_dim_0.out","add_demosaic_2_x___scan_dim_0-1_619.in0"],
["const-1_-1.out","add_demosaic_2_x___scan_dim_0-1_619.in1"],
["and_619_620_621.in0","add_demosaic_2_x___scan_dim_0-1_619.out"],
["count__demosaic_2_x___scan_dim_0.out","add_demosaic_2_x___scan_dim_0-1_659.in0"],
["const-1_-1$2.out","add_demosaic_2_x___scan_dim_0-1_659.in1"],
["and_659_660_661.in0","add_demosaic_2_x___scan_dim_0-1_659.out"],
["count__demosaic_2_x___scan_dim_0.out","add_demosaic_2_x___scan_dim_0-1_684.in0"],
["const-1_-1$4.out","add_demosaic_2_x___scan_dim_0-1_684.in1"],
["and_684_685_686.in0","add_demosaic_2_x___scan_dim_0-1_684.out"],
["count__demosaic_2_y___scan_dim_1.out","add_demosaic_2_y___scan_dim_1-1_623.in0"],
["const-1_-1$1.out","add_demosaic_2_y___scan_dim_1-1_623.in1"],
["and_623_620_624.in0","add_demosaic_2_y___scan_dim_1-1_623.out"],
["count__demosaic_2_y___scan_dim_1.out","add_demosaic_2_y___scan_dim_1-1_675.in0"],
["const-1_-1$3.out","add_demosaic_2_y___scan_dim_1-1_675.in1"],
["and_675_660_676.in0","add_demosaic_2_y___scan_dim_1-1_675.out"],
["count__demosaic_2_y___scan_dim_1.out","add_demosaic_2_y___scan_dim_1-1_688.in0"],
["const-1_-1$5.out","add_demosaic_2_y___scan_dim_1-1_688.in1"],
["and_688_685_689.in0","add_demosaic_2_y___scan_dim_1-1_688.out"],
["const1__620$3.out","and_619_620_621.in1"],
["eq_6210_622.in0","and_619_620_621.out"],
["const1__620$4.out","and_623_620_624.in1"],
["eq_6240_625.in0","and_623_620_624.out"],
["const1__660.out","and_659_660_661.in1"],
["eq_6610_662.in0","and_659_660_661.out"],
["const1__660$1.out","and_675_660_676.in1"],
["eq_6760_677.in0","and_675_660_676.out"],
["const1__685.out","and_684_685_686.in1"],
["eq_6860_687.in0","and_684_685_686.out"],
["const1__685$1.out","and_688_685_689.in1"],
["eq_6890_690.in0","and_688_685_689.out"],
["const1__632.out","ashr_631_632_633.in1"],
["mux_622_626_634.in0","ashr_631_632_633.out"],
["const1__632$1.out","ashr_640_632_641.in1"],
["mux_622_642_656.in1","ashr_640_632_641.out"],
["const2__654.out","ashr_653_654_655.in1"],
["mux_622_642_656.in0","ashr_653_654_655.out"],
["const2__678.out","ashr_674_678_679.in1"],
["mux_662_663_680.in0","ashr_674_678_679.out"],
["mux_662_680_663.in1","ashr_674_678_679.out"],
["const2__702.out","ashr_701_702_703.in1"],
["mux_687_704_712.in1","ashr_701_702_703.out"],
["const1__710.out","ashr_709_710_711.in1"],
["mux_687_704_712.in0","ashr_709_710_711.out"],
["const1__710$1.out","ashr_718_710_719.in1"],
["mux_687_720_721.in1","ashr_718_710_719.out"],
["const1__729.out","ashr_728_729_730.in1"],
["const1__729$1.out","ashr_737_729_738.in1"],
["const1__729$2.out","ashr_741_729_742.in1"],
["self.out.0.0.0","ashr_741_729_742.out"],
["const1__749.out","ashr_748_749_750.in1"],
["const1__749$1.out","ashr_757_749_758.in1"],
["const1__749$2.out","ashr_761_749_762.in1"],
["self.out.0.0.1","ashr_761_749_762.out"],
["const1__769.out","ashr_768_769_770.in1"],
["const1__769$1.out","ashr_777_769_778.in1"],
["const1__769$2.out","ashr_781_769_782.in1"],
["self.out.0.0.2","ashr_781_769_782.out"],
["eq_6240_625.in1","const0_0$1.out"],
["eq_6610_662.in1","const0_0$2.out"],
["eq_6760_677.in1","const0_0$3.out"],
["eq_6860_687.in1","const0_0$4.out"],
["eq_6890_690.in1","const0_0$5.out"],
["eq_6210_622.in1","const0_0.out"],
["count__demosaic_2_x___scan_dim_0_wen.out","count__demosaic_2_x___scan_dim_0.en"],
["count__demosaic_2_x___scan_dim_0_reset.out","count__demosaic_2_x___scan_dim_0.reset"],
["count__demosaic_2_y___scan_dim_1_wen.out","count__demosaic_2_y___scan_dim_1.en"],
["count__demosaic_2_y___scan_dim_1_reset.out","count__demosaic_2_y___scan_dim_1.reset"],
["mux_622_626_634.sel","eq_6210_622.out"],
["mux_622_642_656.sel","eq_6210_622.out"],
["mux_625_635_657.sel","eq_6240_625.out"],
["mux_662_663_680.sel","eq_6610_662.out"],
["mux_662_680_663.sel","eq_6610_662.out"],
["mux_677_681_682.sel","eq_6760_677.out"],
["mux_687_704_712.sel","eq_6860_687.out"],
["mux_687_720_721.sel","eq_6860_687.out"],
["mux_690_713_722.sel","eq_6890_690.out"],
["mux_625_635_657.out","lb_demosaic_2_stencil_update_stream.in.0.0.0"],
["mux_677_681_682.out","lb_demosaic_2_stencil_update_stream.in.0.0.1"],
["mux_690_713_722.out","lb_demosaic_2_stencil_update_stream.in.0.0.2"],
["lb_demosaic_2_stencil_update_stream_wen.out","lb_demosaic_2_stencil_update_stream.wen"],
["self.in.arg_1","lb_padded_2_stencil_update_stream.in"],
["mux_622_626_634.in1","lb_padded_2_stencil_update_stream.out.1.1"],
["mux_662_663_680.in1","lb_padded_2_stencil_update_stream.out.1.1"],
["mux_662_680_663.in0","lb_padded_2_stencil_update_stream.out.1.1"],
["mux_687_720_721.in0","lb_padded_2_stencil_update_stream.out.1.1"],
["lb_padded_2_stencil_update_stream_wen.out","lb_padded_2_stencil_update_stream.wen"],
["mux_625_635_657.in1","mux_622_626_634.out"],
["mux_625_635_657.in0","mux_622_642_656.out"],
["mux_677_681_682.in0","mux_662_663_680.out"],
["mux_677_681_682.in1","mux_662_680_663.out"],
["mux_690_713_722.in1","mux_687_704_712.out"],
["mux_690_713_722.in0","mux_687_720_721.out"]
]
}
}
}
}
}
Constants not properly duplicated
See attached. There are two constants that connect to more than one PE instance.
harrisv.txt
ERROR: NYI: subselecting from a primitive
❯ cgra-mapper test_DefineSub16.json test_DefineSub16_mapped.json
Loading test_DefineSub16.json
Running Pass: rungenerators
In Run Generators
Done running generators
Running Pass: verifyinputconnections
Running Pass: verifyconnectivity-onlyinputs-noclkrst
Running Pass: removebulkconnections
Running Pass: verifycanmap
ERROR: NYI: subselecting from a primitive
0 cgra-mapper 0x0000000104ef7e37 _ZN12MapperPasses12VerifyCanMap13runOnInstanceEPN6CoreIR8InstanceE + 4455
1 libcoreir.dylib 0x0000000105351c37 _ZN6CoreIR11PassManager15runInstancePassEPNS_4PassE + 4103
2 libcoreir.dylib 0x0000000105352f7a _ZN6CoreIR11PassManager7runPassEPNS_4PassE + 442
3 libcoreir.dylib 0x00000001053563c3 _ZN6CoreIR11PassManager3runENSt3__16vectorINS1_12basic_stringIcNS1_11char_traitsIcEENS1_9allocatorIcEEEENS6_IS8_EEEESA_ + 5075
4 libcoreir.dylib 0x0000000105191996 _ZN6CoreIR7Context9runPassesENSt3__16vectorINS1_12basic_stringIcNS1_11char_traitsIcEENS1_9allocatorIcEEEENS6_IS8_EEEESA_ + 150
5 cgra-mapper 0x0000000104f1cb81 main + 10737
6 libdyld.dylib 0x00007fff6f55f115 start + 1
DefineSub16.json
{"top":"global.Sub16",
"namespaces":{
"global":{
"modules":{
"Add16_cin":{
"type":["Record",[
["I0",["Array",16,"BitIn"]],
["I1",["Array",16,"BitIn"]],
["O",["Array",16,"Bit"]],
["CIN","BitIn"]
]],
"instances":{
"bit_const_GND":{
"modref":"corebit.const",
"modargs":{"value":["Bool",false]}
},
"inst0":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
},
"inst1":{
"genref":"coreir.add",
"genargs":{"width":["Int",16]}
}
},
"connections":[
["bit_const_GND.out","inst1.in0.1"],
["bit_const_GND.out","inst1.in0.10"],
["bit_const_GND.out","inst1.in0.11"],
["bit_const_GND.out","inst1.in0.12"],
["bit_const_GND.out","inst1.in0.13"],
["bit_const_GND.out","inst1.in0.14"],
["bit_const_GND.out","inst1.in0.15"],
["bit_const_GND.out","inst1.in0.2"],
["bit_const_GND.out","inst1.in0.3"],
["bit_const_GND.out","inst1.in0.4"],
["bit_const_GND.out","inst1.in0.5"],
["bit_const_GND.out","inst1.in0.6"],
["bit_const_GND.out","inst1.in0.7"],
["bit_const_GND.out","inst1.in0.8"],
["bit_const_GND.out","inst1.in0.9"],
["inst0.in0","inst1.out"],
["inst0.in1","self.I1"],
["inst0.out","self.O"],
["inst1.in1","self.I0"],
["self.CIN","inst1.in0.0"]
]
},
"Invert16_wrapped":{
"type":["Record",[
["I",["Array",16,"BitIn"]],
["O",["Array",16,"Bit"]]
]],
"instances":{
"inst0":{
"genref":"coreir.not",
"genargs":{"width":["Int",16]}
}
},
"connections":[
["inst0.in","self.I"],
["inst0.out","self.O"]
]
},
"Sub16":{
"type":["Record",[
["I0",["Array",16,"BitIn"]],
["I1",["Array",16,"BitIn"]],
["O",["Array",16,"Bit"]]
]],
"instances":{
"bit_const_VCC":{
"modref":"corebit.const",
"modargs":{"value":["Bool",true]}
},
"inst0":{
"modref":"global.Invert16_wrapped"
},
"inst1":{
"modref":"global.Add16_cin"
}
},
"connections":[
["bit_const_VCC.out","inst1.CIN"],
["inst0.I","self.I1"],
["inst0.O","inst1.I1"],
["inst1.I0","self.I0"],
["inst1.O","self.O"]
]
}
}
}
}
}
Improve tool interoperability
Finish Const folding
Fix IOs to not depend on width=16, but to depend on if there are selects
Add support for signed less than?
slt is needed for harris
Cannot find libcoreir-cgralib.so
I'm using CGRAMapper dev and coreir dev on kiwi. When I try to run it I get this error:
dhuff@kiwi:~/CGRAGenerator/bitstream/bsbuilder/testdir$ ~/CGRAMapper/bin/cgra-mapper examples/harris.json harris_mapped.json
/horowitz/users/dhuff/CGRAMapper/bin/cgra-mapper: error while loading shared libraries: libcoreir-cgralib.so: cannot open shared object file: No such file or directory@rdaly525 do you know what this error is?
Incorrect mux logic
Implementation of mux in the PE tile (see cgra_info.txt in CGRAGenerator repo):
<op sel='0x08' name='sel'>
pe_out_res=op_d?op_a:op_b
comp_res_p=(op_a+op_b) gte 2^16
</op>It seems that CoreIR is assuming if selection bit bit0 == 0, outputs data0, which is consistent with most logic designs (I made that assumption too early on when debugging).
An easy and dirty fix would be swapping data.in.0 and data.in.1 in the mux pass, but it would be nice for the mapper to parse cgra_info.txt in the future so that it could generate netlists against different targets.
I can send a pull request to swap two operands if you want, but I'd like to do that based on your suggestion.
concat NYI
While trying to map the demosiac app, it errors out with
ERROR: NYI mapping primitive corebit.concat. Needs to be a module with def!
The json is below. Note that no concat exists in the json originally.
demosaic_premapped.txt
`alu_op_debug` max/smax incorrect
See
CGRAMapper/src/definitions/cgralib_def.h
Line 39 in b9ab907
The debug string should be smax.
I'm wondering what's the future plan for alu_op_debug? It's useful to me since I don't need to regenerate the same string as the mapper already does that. But if you want to remove it in the future, I can copy your code over to my PnR tools. Is there any documentation on how these bits are translated to op str? Thanks.
travis memory leak issue when running tests together
I'm not exactly sure what the problem in CoreIR is, but due to a memory leak issue, many tests in the garnet repo cannot be run together with pytest in travis. The tests fail with the message "OSError: [Errno 12] Cannot allocate memory". Here is a link to a build where all the tests fail because of this issue: https://travis-ci.com/github/StanfordAHA/garnet/builds/166559370. To bypass this issue, Keyi split up how the tests are run in the garnet repo in the run.sh script for travis. However, as we add more tests, we keep running into this, so tests have been moved out of test_interconnect to minimize the memory leak but we'd like to move them back in there to test the memory tile with the interconnect if possible. Thanks! (Also not completely sure who to assign to the issue, please feel free to change).
eq test does not map
Below is the error message after trying to map the new eq test (which tests both eq and neq ops):
eq_premapped.txt
Running Pass: rungenerators
In Run Generators
Done running generators
Running Pass: verifyinputconnections
Running Pass: verifyconnectivity-onlyinputs-noclkrst
Running Pass: removebulkconnections
Running Pass: verifyinputconnections
Running Pass: verifycanmap
Running Pass: deletedeadinstances
Running Pass: createfullinstancemap
Running Pass: removewires
Running Pass: verifyinputconnections
Running Pass: cullgraph
Running Pass: verifyinputconnections
Running Pass: createinstancegraph
Running Pass: verifytechmapping
Module: wire
Type: {'in':BitIn, 'out':Bit}
Def? No
ERROR: NYI mapping primitive corebit.wire. Needs to be a module with def!
travis test fails on master (and all other branches?)
See e.g. travis build 373
https://travis-ci.org/StanfordAHA/CGRAMapper/builds/478549330
Special mapper for taped out CGRA that deals with the bugs
No 16-bit NOT in PE implementation
We don't actually have 16-bit NOT in the current PE implementation, despite that it's somewhere in the hardware spec. Depends on what's implemented in CoreIR, we need to replace it with either a comparator or an XOR.
Update _stereo.json with new mux types?
With muxN widths fixed there is a new problem.
The stereo example now has type errors because the input connections to muxN selects are too large. For example
bash-3.2$ ~/CppWorkspace/coreir/bin/coreir -i ~/CppWorkspace/CGRAMapper/examples/_stereo.json -p rungenerators --load_libs ~/CppWorkspace/coreir/lib/libcoreir-commonlib.dylib
ERROR: DesignTop: Cannot wire together
add_1438810_15141.out : Bit[16]
_pass_7_stencil0_mux71_0$199.in.sel : BitIn[7]
ERROR: DesignTop: Cannot wire together
add_1438810_15141.out : Bit[16]
_pass_7_stencil0_mux71_0$207.in.sel : BitIn[7]
ERROR: DesignTop: Cannot wire together
add_1438810_15141.out : Bit[16]
_pass_7_stencil0_mux71_0$215.in.sel : BitIn[7]
ERROR: DesignTop: Cannot wire together
add_1438810_15141.out : Bit[16]
_pass_7_stencil0_mux71_0$223.in.sel : BitIn[7]
ERROR: DesignTop: Cannot wire together
add_1438810_15141.out : Bit[16]
_pass_7_stencil0_mux71_0$231.in.sel : BitIn[7]
ERROR: DesignTop: Cannot wire together
add_1438810_15141.out : Bit[16]
_pass_7_stencil0_mux71_0$239.in.sel : BitIn[7]
ERROR: DesignTop: Cannot wire together
add_1438810_15141.out : Bit[16]
_pass_7_stencil0_mux71_0$247.in.sel : BitIn[7]
ERROR: DesignTop: Cannot wire together
add_1438810_15141.out : Bit[16]
_pass_7_stencil0_mux71_0$255.in.sel : BitIn[7]
I AM DYING!
Assertion failed: (0), function die, file context.cpp, line 105.
Abort trap: 6@jeffsetter Could you update the stereo code generation with slices to fix this?
Always Pull The Latest CoreIR Without Using Version Numbers
Make the compiler/mapper aware of the new PE spec
Modes for IO
To converge with CGRA info it would preferable if the modes for IO were "in" and "out" instead of "i" and "o"
Orphaned registers
I'm trying to PnR fast-corner that Jeff had, which has passed CoreIR test. In the mapped netlist, there are some orphaned registers that take input but don't drive any nets. For instance, you can search for lb_p4_hw_in_stencil_update_stream$lb_recurse$lb1d_6$reg_6. We only have this connection:
["lb_p4_hw_in_stencil_update_stream$lb_recurse$lb1d_6$reg_6.in","lb_p4_hw_in_stencil_update_stream$lb_recurse$lb1d_6$reg_5.out"]
I can run a pass on my end to remove any orphaned node other than IOs, but I'd prefer this get's fixed in the mapper. Maybe there is a pass in CoreIR already but not enabled by default in the mapper.
Using the build from master branch. Input and output attached.
Cascade fails
The mapper fails on the cascade app (3x3 convolution followed by another 3x3 convolution).
Travis:
https://travis-ci.org/StanfordAHA/CGRAFlow/jobs/416473662
First Error:
ERROR I don't know what 'mul_49919.in0' is
Traceback (most recent call last):
File "CGRAGenerator/testdir/graphcompare/json2dot.py", line 339, in
tf1 = to_or_from(k[1]);
File "CGRAGenerator/testdir/graphcompare/json2dot.py", line 249, in to_or_from
assert False
AssertionError
cascade design attached as txt (change to json)
cascade_design_top.txt
ERROR: Args and params are not the same!
Args: (alu_op:inv,
data0_mode:BYPASS,
data0_value:16'h0000,
data1_mode:BYPASS,
data1_value:16'h0000,
signed:False)
Params: (alu_op:BitVector<6>,
alu_op_debug:String,
data0_mode:String,
data0_value:BitVector<16>,
data1_mode:String,
data1_value:BitVector<16>,
signed:BitVector<1>)
binop
Using CoreIR dev and Mapper dev.
I was trying out demosaic and it seems that some of the function signature was not updated. Test file included.demosaic.txt
Flatten types is not sufficient for all usecases
I should update the passes to do:
rungenerators
verifyinputconnections
removebulkconnections
verifycanmap
-Verifies that all the instances are coreir, linebuffer, or module defs (not concat or slice)
-For leaf instances, verify there are no selects from below the top record
verifylinebufferboundaries
Match target set of ops generated by Halide
Don't invent new ones until needed
Deal with slice and concat
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