Comments (3)
Kuree
commented on September 23, 2024
- mux fix (flip
selsignal). -
ashris not working. We need to create extra logic to handle this. - 1bit IO input is not working. This either requires a 16-to-1 converter or using JTAG stall. @leonardt can you and Ross discuss how to handle this bug gracefully?
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rdaly525
commented on September 23, 2024
What does 1bit IO input not working mean? Does this mean that we need to burn 16 bits of input to access a single bit?
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Kuree
commented on September 23, 2024
That is correct. You might also need a comparator to reduce the input to a single bit so that the rest of the chip can use it.
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Related Issues (20)
- Add support for signed less than? HOT 2
- Cannot find libcoreir-cgralib.so HOT 3
- ERROR: NYI using mutliple memories
- Cascade fails HOT 1
- Constants not properly duplicated HOT 4
- Incorrect mux logic HOT 1
- `alu_op_debug` max/smax incorrect HOT 1
- Requires to be installed HOT 1
- Mapper doesn't handle ashr properly
- No 16-bit NOT in PE implementation HOT 1
- concat NYI HOT 2
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- Make the compiler/mapper aware of the new PE spec
- Improve tool interoperability
- Match target set of ops generated by Halide HOT 3
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- Orphaned registers HOT 1
- travis test fails on master (and all other branches?)
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