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  • 👋 Hi, I’m @smosanu
  • 👀 I’m interested in FPGA projects, computer architecture emulation, RISC-V, machine learning / artificial intelligence / generative AI, high performance computing, embedded and IoT systems and applications, and other cool concepts
  • 🌱 I’m currently learning and experimenting with generative AI, and trying to contribute from the architecture side of things, plus I'm preparing for technical interviews and working on a paper related to my Ph.D. thesis
  • 💞️ I’m looking for new opportunities, work on AI, computer architecture, FPGA and other related fields
  • 📫 Reach me on twitter @smosanu or email me.

Sergiu Mosanu's Projects

experimental_fpga_computer icon experimental_fpga_computer

This code implements a switch for interconnecting 50 FPGA boards in a topology based on the Hoffman–Singleton graph

interviewing icon interviewing

General coding exercises in preparation for technical interviews

litedram icon litedram

Small footprint and configurable DRAM core

litex icon litex

Build your hardware, easily!

migen icon migen

A Python toolbox for building complex digital hardware

pp4fpgas icon pp4fpgas

Parallel Programming for FPGAs -- An open-source high-level synthesis book

ramulator icon ramulator

A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, WIOx, HBMx, and various academic proposals. Described in the IEEE CAL 2015 paper by Kim et al. at http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf

smosanu icon smosanu

Config files for my GitHub profile.

trie-python-graphviz icon trie-python-graphviz

This is an Object Oriented implementation of a Trie in python. The class contains setter and getter methods, and implements several useful functionalities. In addition, the class can generate graphviz dot code, which can be used to visualize the Trie.

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