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Seems a lot of logic can be saved and cleaned if we add those 2 signals to the control function.

Tafas, eu nao to conseguindo botar o mestre pra ler mais de 1 word. Pra isso acontecer tenho que mudar umas coisas no spi_control_mq.
Um exemplo é em:

when inc_addr_st =>   
     case command is
           when WRITE_c       =>
             tmp := wait4spi_st;
           when FAST_WRITE_c  =>
             tmp := wait4spi_st;
           when READ_c        =>
             tmp := read_st;
           when FAST_READ_c   =>
             tmp := read_st;
           when others        =>
             tmp := wait_forever_st;
         end case;

trocar o estado read_st por act_st. O read_st nao faz nada na maquina de estados, e aí depois de incrementar o endereco, a maquina de estados vai pra wait_forever_st

If my slave leaves the xRESP signal in an error state when in Idle, during the next operation, the master will accuse error immediately, not waiting for the xVALID signal to go high.

if M_AXI_BVALID = '1' and M_AXI_BRESP(1) = '0' then
mst_exec_state <= BUS_DONE;
M_AXI_BREADY <= '0';
elsif M_AXI_BRESP(1) = '1' then
mst_exec_state <= BUS_DONE;
M_AXI_BREADY <= '0';
bus_error_o <= '1';
else
mst_exec_state <= INIT_WRITE;
end if;`

I changed the behavior of the slave to keep the RESP in OK when idle, and only set the error when VALID is high, then it works ok, but should this piece of the AXI master be changed?

When i try to run synthesis, vivado tells me the following:
[Synth 8-26] attribute 'event not implemented [spi_slave.vhd:144]

it is this line here:
elsif spck_s = edge_s and spck_s'event then

when i make edge_s as a constant, it works ok

Must look for #8

Instead of adding data_word_size, figure how many addr_v bits will always be zero and keep adding just 1.

Opa, to tentando usar o fast_read aqui e aparentemente ele nao faz a leitura no AXI-M, só fica jogando o ACK pra fora
fiz uma simulacao, segue o waveform (já que voce gosta muito de waveform :) ):

to fazendo alguma coisa errada?

Native clock mode used an latch on output as means to give as much time as possible to AXI Bus to respond. Since oversampled mode has MCK>8*SPCK, probably this latch won't be necessary.

One good improvement is to have this as a flipflop on oversampled mode instead of a latch.

Hi, me again
what is the theoretical max sclk frequency for this block? In native and in oversampled modes.

In my tests, axi clk is 100 Mhz, with sclk in 12 MHz the reads lose the first byte for each word. There is a latency in between the act_st and the wait4spi_st (when it puts the value on spi_txdata_o). When the spi is a bit faster, this is enough for the state machine to lose the first spi_txen_i = 1.
In the oversampled mode only the fast read is working in my tests. In the normal read, the first bit in the first byte can come wrong, but i did not have time to investigate it.