Name: Ricardo F Tafas Jr
Type: User
Company: @espressif
Bio: Eletrical Engineer, MSC on Telecomunication, several times manager and Developer. Specialty on Hardware, HDLs (mostly VHDL and SysVerilog). Sometimes writer.
Twitter: rftafas
Location: Campinas - SP
Blog: www.repositorio.blog
Ricardo F Tafas Jr's Projects
VHDL package to provide C-like string formatting
Simple parser for extracting VHDL documentation
Python VHDL code generators
A collection for basic digital implementations used for building more complex IPs.
Standard and Curated cores, tested and working.
A numeric_std compatible replacement for std_logic_arith and std_logic_unsigned
VHDL High Level Synthesis is a library with some constructions to enable higher level usage of VHDL. Should work on synthesis.
VUnit is a unit testing framework for VHDL/SystemVerilog