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View Code? Open in Web Editor NEWPython VHDL code generators
License: Apache License 2.0
Python VHDL code generators
License: Apache License 2.0
No declaration for bresp_timer_sr in the generated .vhd
add support for Protected Types both on entities and on packages.
Tafas,
I tried to use the regbank.py script to generate a register bank, but It seems the port declarantion in the entity is wrong. Here is an abstract of my script:
myregbank = registerBank("ssvectors_reg","rtl",32,5)
myregbank.add(0,"control")
myregbank.reg[0].add("control_own_addr","ReadWrite",0,4)
myregbank.reg[0].add("control_rx_buffer","ReadWrite",4,2)
myregbank.reg[0].add("control_send_type","ReadWrite",6,4)
myregbank.reg[0].add("control_state","ReadWrite",10,3)
myregbank.reg[0].add("control_rsv","ReadWrite",13,19)
and I get the following entity declaration :
entity ssvectors_reg is
generic (
C_S_AXI_ADDR_WIDTH : integer := 3;
C_S_AXI_DATA_WIDTH : integer := 32
);
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
control_own_addr_o : out std_logic_vector(3 downto 0);
control_rx_buffer_o : out std_logic_vector(1 downto 0);
control_send_type_o : out std_logic_vector(3 downto 0);
control_state_o : out std_logic_vector(2 downto 0);
control_rsv_o : out std_logic_vector(18 downto 0);
control_own_addr_o(3 downto 0) : out std_logic_vector(3 downto 0);
control_rx_buffer_o(1 downto 0) : out std_logic_vector(1 downto 0);
control_send_type_o(3 downto 0) : out std_logic_vector(3 downto 0);
control_state_o(2 downto 0) : out std_logic_vector(2 downto 0);
control_rsv_o(18 downto 0) : out std_logic_vector(18 downto 0)
);
end ssvectors_reg;
Note how the registers are doubled in the declaration. E.g.:
control_rx_buffer_o : out std_logic_vector(1 downto 0);
(...)
control_rx_buffer_o(1 downto 0) : out std_logic_vector(1 downto 0);
Is there a problem here in the script or did I misused it?
Cheers,
Tomas
`
I wrote a Test bench to verify the design and had problems in both read and write transactions.
In the screenshot below, the corresponding reg_i field gets a random value and the test bench tries to read it using the axi interface. As you can see in the screenshot below, rdata does not change:
When the Test Bench tries to write to a register, all fields of regwrite_s get the same value, as waveforms of the screenshot below illustrate:
You can get the simulation files in my personal repository (https://github.com/tpcorrea/hdltools/tree/records). The Test Bench uses VUnit and UVVM with GHDL simulator. To use UVVM, you have to compile the necessary libraries and correct the run.py file to point to the correct compiled library path.
use the "Incomplete Custom Type" to add generic types to entity generic declaration field.
on the regbank script:
the function calling for code creation .code() sets a flag to not create ports more than once. One can clean this flag several ways, one suggestion is to clean it everytime add_register is called.
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