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   myregbank = registerBank("ssvectors_reg","rtl",32,5)

    myregbank.add(0,"control")
    myregbank.reg[0].add("control_own_addr","ReadWrite",0,4)
    myregbank.reg[0].add("control_rx_buffer","ReadWrite",4,2)
    myregbank.reg[0].add("control_send_type","ReadWrite",6,4)
    myregbank.reg[0].add("control_state","ReadWrite",10,3)
    myregbank.reg[0].add("control_rsv","ReadWrite",13,19)

entity ssvectors_reg is

  generic (

    C_S_AXI_ADDR_WIDTH : integer := 3;

    C_S_AXI_DATA_WIDTH : integer := 32

  );

  port (

    S_AXI_ACLK : in std_logic;

    S_AXI_ARESETN : in std_logic;

    S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);

    S_AXI_AWPROT : in std_logic_vector(2 downto 0);

    S_AXI_AWVALID : in std_logic;

    S_AXI_AWREADY : out std_logic;

    S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);

    S_AXI_WVALID : in std_logic;

    S_AXI_WREADY : out std_logic;

    S_AXI_BRESP : out std_logic_vector(1 downto 0);

    S_AXI_BVALID : out std_logic;

    S_AXI_BREADY : in std_logic;

    S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);

    S_AXI_ARPROT : in std_logic_vector(2 downto 0);

    S_AXI_ARVALID : in std_logic;

    S_AXI_ARREADY : out std_logic;

    S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);

    S_AXI_RRESP : out std_logic_vector(1 downto 0);

    S_AXI_RVALID : out std_logic;

    S_AXI_RREADY : in std_logic;

    control_own_addr_o : out std_logic_vector(3 downto 0);

    control_rx_buffer_o : out std_logic_vector(1 downto 0);

    control_send_type_o : out std_logic_vector(3 downto 0);

    control_state_o : out std_logic_vector(2 downto 0);

    control_rsv_o : out std_logic_vector(18 downto 0);

    control_own_addr_o(3 downto 0) : out std_logic_vector(3 downto 0);

    control_rx_buffer_o(1 downto 0) : out std_logic_vector(1 downto 0);

    control_send_type_o(3 downto 0) : out std_logic_vector(3 downto 0);

    control_state_o(2 downto 0) : out std_logic_vector(2 downto 0);

    control_rsv_o(18 downto 0) : out std_logic_vector(18 downto 0)

  );

end ssvectors_reg;