This repository has been archived. A fully AXI compliant replacement for this interconnect can be found in pulp-platform/axi.
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AXI X-Bar
License: Other
This repository has been archived. A fully AXI compliant replacement for this interconnect can be found in pulp-platform/axi.
Having a hint that all is not well with the crossbar, I tried simulating in the verification environment that is provided for Xilinx crossbar. The Xilinx crossbar passes but this one gives the following errors:
(The references to PASSED refer to the Xilinx crossbar that runs in parallel for comparison)
A test case is available but after minimisation it was still too large to upload here.
Chronologic VCS simulator copyright 1991-2017
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Compiler version M-2017.03-SP2-5_Full64; Runtime version M-2017.03-SP2-5_Full64; Nov 13 12:07 2018
0: exdes_tb: Starting testbench
0: exdes_tb: System reset detected: 1
2500000: exdes_tb: System reset detected: 0
7885000 : exdes_tb.exdes_top.exdes_top_pulp.genblk1[0].proto_master.inst.REP : BIT( 79) : ERROR : AXI_AUXM_RCAM_UNDERFLOW. Read CAM underflow.
$stop at time 7885000 Scope: exdes_tb.exdes_top.exdes_top_pulp.genblk1[0].proto_master.inst.REP File: ./../../axi_crossbar_0_ex/axi_crossbar_0_ex.ip_user_files/ipstatic/hdl/axi_protocol_checker_v2_0_vl_rfs.sv Line: 5250
ucli% run
7985000 : exdes_tb.exdes_top.exdes_top_pulp.genblk1[0].proto_master.inst.REP : BIT( 58) : ERROR : Invalid state x
7985000 : exdes_tb.exdes_top.exdes_top_pulp.genblk1[0].proto_master.inst.REP : BIT( 59) : ERROR : AXI_ERRS_RID: A slave can only give read data with an ID to match an outstanding read transaction. Spec: section A5.3.1.
$stop at time 7985000 Scope: exdes_tb.exdes_top.exdes_top_pulp.genblk1[0].proto_master.inst.REP File: ./../../axi_crossbar_0_ex/axi_crossbar_0_ex.ip_user_files/ipstatic/hdl/axi_protocol_checker_v2_0_vl_rfs.sv Line: 5230
ucli%
ucli%
ucli% run
8485000 : exdes_tb.exdes_top.exdes_top_pulp.genblk1[0].proto_master.inst.REP : BIT( 32) : ERROR : AXI_ERRS_BRESP_AW: A slave must not give a write response before the write address. Spec: section A3.3.1 and figure A3-7.
$stop at time 8485000 Scope: exdes_tb.exdes_top.exdes_top_pulp.genblk1[0].proto_master.inst.REP File: ./../../axi_crossbar_0_ex/axi_crossbar_0_ex.ip_user_files/ipstatic/hdl/axi_protocol_checker_v2_0_vl_rfs.sv Line: 5203
ucli% run
92085000 : exdes_tb.exdes_top.exdes_top_pulp.genblk1[0].proto_master.inst.REP : BIT( 58) : ERROR : AXI_ERRS_RDATA_NUM: The number of read data items must match the corresponding ARLEN. Spec: section A3.4.1.
$stop at time 92085000 Scope: exdes_tb.exdes_top.exdes_top_pulp.genblk1[0].proto_master.inst.REP File: ./../../axi_crossbar_0_ex/axi_crossbar_0_ex.ip_user_files/ipstatic/hdl/axi_protocol_checker_v2_0_vl_rfs.sv Line: 5229
ucli% run
147090000: exdes_tb: SIMULATION PASSED
147090000: exdes_tb: Test Completed Successfully
$stop at time 147090000 Scope: exdes_tb File: ./../imports/axi_crossbar_0_example_design_tb.v Line: 102
ucli% run
147095000: exdes_tb: SIMULATION PASSED
147095000: exdes_tb: Test Completed Successfully
$stop at time 147095000 Scope: exdes_tb File: ./../imports/axi_crossbar_0_example_design_tb.v Line: 102
ucli% exit
V C S S i m u l a t i o n R e p o r t
Time: 147095000 ps
CPU Time: 1.380 seconds; Data structure size: 3.0Mb
Tue Nov 13 12:07:33 2018
Some industry lint/synth tools do not like that same genvar is used in different for-loops inside the same generate statement.
Currently the way the arbiter is organized can cause the payload of AXI beats (address, data, etc.) to change after the valid
signals has been asserted. This violates the AXI4 standard. Rework the arbiter such that it holds on to its decision until the request is cleared. This should be easily doable by having the round-robin flag jump to the selected master.
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