oskirby / logicbone Goto Github PK

The list of things yet to be tested on the prototype boards before we should start looking into the next revision

• Micro-SD card slot.
• Downstream-Facing USB port detection and power management.
• Downstream-Facing USB port SERDES support (test out https://github.com/enjoy-digital/usb3_pipe)
• Analog-to-Digital converter.
• m.2 PCIe SERDES support.
• Gather noise and current measurements for VCORE and VDDR supplies.
• LiteX support for 2GB memory size.

Chase down supplier links for everything on the board to make sure nothing has magically gone out of stock and to get some estimates on pricing.

It seems that there are three ways in which the ECP5 can reset itself in order to handle multi-boot images:

• VCC, VCCAUX and VCCIO8 rise above their POR thresholds.
• Rising edge on PROGRAMN pin
• Issuing a REFRESH command over SPI slave or JTAG ports.

I was hoping that one of the config ports would have been accessible internally from the FPGA fabric to issue the REFRESH command, but this doesn't appear to be the case so instead we'll need to bodge the board so that the FPGA can pull the PROGRAMN pin.

On the prototypes, we will work around the issue by removing IC12 and bridging ETH_RESET to SYS_RESET. This will allow the ETH_RESET pin to reboot the FPGA, but we loose the ability to reset the ethernet PHY independently of the rest of the system.

A better solution would be to pull SYS_RESET low via one of the unused pins in the DDR3 bank.

MDIO is an open drain bus, and the FPGA's internal pullup is too weak to drive the bus correctly. Adding a 5k pullup allows us to detect and read the MDIO registers.

Hello I am a FPGA developer

If you want to add your board to IceStudio you only have to send me one board, and I am glad to include the board in the supported list of boards of this IDE.

IceStudio is a visual editor for open FPGA boards
https://icestudio.io/

I have already added different boards with ECP5 Lattice Model to ICEStudio
Colorlight boards --> FPGAwars/icestudio#500
FleaFPGA-Ohm ECP5 board --> FPGAwars/icestudio#521
and ECP-5 Evaluation Board --> FPGAwars/icestudio#541

My email is benitoss@gmail,com if you are interested

Rergards
Fernando

While trying to synthesize using LiteDram, we get an error that pin DDR3_DM1 is not located in the same DQS group as the rest of the high DQS bank (it appears to be using a DQSBUFM hard IP to control this signal). This presumeably means that the data mask signals also need to be length matched with their DQS groups too.

The MxL7704 datasheet leaves the purpose of the 5VSYS pin a bit ambiguous as to whether it is internally connected to VIN, or whether it's requires an external RC filter to VIN. Turns out it needs an external RC filter. We can work around it on the prototypes by bodging a 10ohm resistor between 5VSYS and VBUS, but this should be fixed for future production runs.

The caBGA381 is a big package, with a lot of balls. That's a lot of data entry that is ripe for user error and we should take some time to review the pinout to make sure its correct before manufacturing begins.

We also need to pay attention to compatibility between logic sizes, and the ECP5-5G variants to get an idea of which parts can be substituted.

This issue is mostly just to keep a list of parts that we might want to change out if we get a chance.

The 25MHz crystal used to generate the PCIe and DDR3 clocks is coprime with the desired frequency needed for the USB bootloader (48MHz) which leads to some awkwardness in the PLL configuration. In retrospect it may have made more sense to just include a spare 12-ish MHz oscillator for assorted programming uses.

It seems that there is an discrepancy in the Beaglebone Black reference manual, and the schematic. The SRM states that P8 pins 11 through 21 are used for the eMMC and shouldn't be used by the capes when the eMMC is in use, but the Beaglebone schematics show P8 pins 3-6 and 20-25 are used by the eMMC.

Unfortunately, the Logicbone was laid out according to the reference manual, which means that we won't be compatible with capes that make use of P8 pins 11-21 such as the CRAMPS board or 24-bit LCD displays.