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License: BSD 3-Clause "New" or "Revised" License
Demo projects for various Kintex FPGA boards
License: BSD 3-Clause "New" or "Revised" License
I tried processing the litex generated output (with demo based tweaks on generated .xdc file), however it can't generate the bitstream(vivado can process the same w/o error). Here is the error (project source xc7k325t-veriscv-nextpnr.zip ):
Info: Annotating ports with timing budgets for target frequency 50.00 MHz
Info: Checksum: 0x40513b0e
Info: Device utilisation:
Info: SLICE_LUTX: 32144/407600 7%
Info: SLICE_FFX: 18140/407600 4%
Info: CARRY4: 985/50950 1%
Info: PSEUDO_GND: 1/86505 0%
Info: PSEUDO_VCC: 1/86505 0%
Info: HARD0: 0/ 3660 0%
Info: RAMB18E1_RAMB18E1: 41/ 890 4%
Info: FIFO18E1_FIFO18E1: 0/ 445 0%
Info: RAMBFIFO36E1_RAMBFIFO36E1: 0/ 445 0%
Info: RAMB36E1_RAMB36E1: 16/ 445 3%
Info: DSP48E1_DSP48E1: 16/ 840 1%
Info: PAD: 71/ 1460 4%
Info: IOB33M_OUTBUF: 0/ 168 0%
Info: IOB33S_OUTBUF: 0/ 168 0%
Info: IOB33_OUTBUF: 16/ 350 4%
Info: IOB33M_INBUF_EN: 0/ 168 0%
Info: IOB33S_INBUF_EN: 0/ 168 0%
Info: IOB33_INBUF_EN: 13/ 350 3%
Info: IOB33M_TERM_OVERRIDE: 0/ 168 0%
Info: IOB33S_TERM_OVERRIDE: 0/ 168 0%
Info: IOB33_TERM_OVERRIDE: 0/ 350 0%
Info: PULL_OR_KEEP1: 0/ 980 0%
Info: IDELAYE2_IDELAYE2: 16/ 500 3%
Info: OLOGICE3_TFF: 0/ 350 0%
Info: OLOGICE3_OUTFF: 8/ 350 2%
Info: OLOGICE3_MISR: 0/ 350 0%
Info: OSERDESE2_OSERDESE2: 44/ 500 8%
Info: ILOGICE3_IFF: 4/ 350 1%
Info: ILOGICE3_ZHOLD_DELAY: 0/ 350 0%
Info: ISERDESE2_ISERDESE2: 16/ 500 3%
Info: BUFIO_BUFIO: 0/ 40 0%
Info: IDELAYCTRL_IDELAYCTRL: 1/ 10 10%
Info: BUFGCTRL: 7/ 32 21%
Info: SELMUX2_1: 37/154550 0%
Info: BUFG_BUFG: 0/ 32 0%
Info: BUFHCE_BUFHCE: 0/ 168 0%
Info: PLLE2_ADV_PLLE2_ADV: 1/ 10 10%
Info: INVERTER: 3/ 240 1%
Info: BUFFER: 0/ 480 0%
Info: ILOGICE2_IFF: 0/ 500 0%
Info: OLOGICE2_MISR: 0/ 500 0%
Info: OLOGICE2_OUTFF: 0/ 500 0%
Info: OLOGICE2_TFF: 0/ 500 0%
Info: IOB18_INBUF_DCIEN: 16/ 150 10%
Info: IOB18_OUTBUF_DCIEN: 41/ 150 27%
Info: IOB18_TERM_OVERRIDE: 0/ 150 0%
Info: IOB18S_INBUF_DCIEN: 0/ 72 0%
Info: IOB18S_OUTBUF_DCIEN: 3/ 72 4%
Info: IOB18S_TERM_OVERRIDE: 0/ 72 0%
Info: IOB18M_INBUF_DCIEN: 2/ 72 2%
Info: IOB18M_OUTBUF_DCIEN: 3/ 72 4%
Info: IOB18M_TERM_OVERRIDE: 0/ 72 0%
Info: IDELAYE2_FINEDELAY_IDELAYE2_FINEDELAY: 0/ 150 0%
Info: ODELAYE2_ODELAYE2: 0/ 150 0%
ERROR: Cell 'ODDR_2' cannot be bound to bel 'OLOGIC_X0Y147/OUTFF' since it is already bound to cell 'ODDR_3'
0 warnings, 1 error
make: *** [Makefile:41: qmtech_kintex.fasm] Error 255
openXC7 0.7.0 update (more specifically yosys) introduces a build regression for litex-ddr-kc705 and litex-ddr-hpcstore-k420t demos due to unsupported inference of RAM128X1S/RAM256X1S (LUTRAM/Distributed RAM) primitives.
Info: Device utilisation:
Info: SLICE_LUTX: 12586/407600 3%
Info: SLICE_FFX: 6139/407600 1%
Info: CARRY4: 369/50950 0%
Info: PSEUDO_GND: 1/86505 0%
Info: PSEUDO_VCC: 1/86505 0%
Info: HARD0: 0/ 3660 0%
Info: RAMB18E1: 8/ 890 0%
Info: FIFO18E1: 0/ 445 0%
Info: RAMBFIFO36E1: 0/ 445 0%
Info: RAMB36E1: 11/ 445 2%
Info: DSP48E1: 4/ 840 0%
Info: PAD: 131/ 1460 8%
Info: IOB33M_OUTBUF: 0/ 168 0%
Info: IOB33S_OUTBUF: 0/ 168 0%
Info: IOB33_OUTBUF: 5/ 350 1%
Info: IOB33M_INBUF_EN: 0/ 168 0%
Info: IOB33S_INBUF_EN: 0/ 168 0%
Info: IOB33_INBUF_EN: 3/ 350 0%
Info: IOB33M_TERM_OVERRIDE: 0/ 168 0%
Info: IOB33S_TERM_OVERRIDE: 0/ 168 0%
Info: IOB33_TERM_OVERRIDE: 0/ 350 0%
Info: PULL_OR_KEEP1: 0/ 980 0%
Info: IDELAYE2: 64/ 500 12%
Info: OLOGICE3_TFF: 0/ 350 0%
Info: OLOGICE3_OUTFF: 0/ 350 0%
Info: OLOGICE3_MISR: 0/ 350 0%
Info: OSERDESE2: 107/ 500 21%
Info: ILOGICE3_IFF: 0/ 350 0%
Info: ILOGICE3_ZHOLD_DELAY: 0/ 350 0%
Info: ISERDESE2: 64/ 500 12%
Info: BUFIO: 0/ 40 0%
Info: IDELAYCTRL: 3/ 10 30%
Info: BUFGCTRL: 4/ 32 12%
Info: BSCAN: 0/ 4 0%
Info: BUFG: 0/ 32 0%
Info: DCIRESET: 0/ 1 0%
Info: DNA_PORT: 0/ 1 0%
Info: EFUSE_USR: 0/ 1 0%
Info: FRAME_ECC: 0/ 1 0%
Info: ICAP: 0/ 2 0%
Info: INVERTER: 9/ 240 3%
Info: IOB18M_OUTBUF_DCIEN: 9/ 72 12%
Info: IOB18_INBUF_DCIEN: 65/ 150 43%
Info: IOB18_OUTBUF_DCIEN: 102/ 150 68%
Info: MMCME2_ADV: 0/ 10 0%
Info: ODELAYE2: 107/ 150 71%
Info: OLOGICE2_TFF: 0/ 500 0%
Info: OLOGICE2_OUTFF: 0/ 500 0%
Info: PLLE2_ADV: 1/ 10 10%
Info: SELMUX2_1: 4/154550 0%
Info: STARTUP: 0/ 1 0%
Info: USR_ACCESS: 0/ 1 0%
Info: BUFHCE: 0/ 168 0%
Info: BUFFER: 0/ 480 0%
Info: ILOGICE2_IFF: 0/ 500 0%
Info: OLOGICE2_MISR: 0/ 500 0%
Info: IOB18_TERM_OVERRIDE: 0/ 150 0%
Info: IOB18S_INBUF_DCIEN: 0/ 72 0%
Info: IOB18S_OUTBUF_DCIEN: 9/ 72 12%
Info: IOB18S_TERM_OVERRIDE: 0/ 72 0%
Info: IOB18M_INBUF_DCIEN: 9/ 72 12%
Info: IOB18M_TERM_OVERRIDE: 0/ 72 0%
Info: IDELAYE2_FINEDELAY: 0/ 150 0%
Info: Placed 687 cells based on constraints.
ERROR: Unable to place cell 'data_mem_grain0.0.0.genblk1.genblk1[0].genblk1.slice', no Bels remaining of type 'RAM128X1S'
0 warnings, 1 error
make: *** [../openXC7.mk:40: xilinx_kc705.fasm] Error 255
Looks like the openXC7 0.7.0 release includes an update to yosys 0.36 (from 0.17), which introduces memory_libmap
pass (from 0.18 release). Reverting YosysHQ/yosys@3b2f959 stops yosys from inferring unsupported LUTRAM primitives.
Can you add the script/command used to generate the litex builds? I can't my own builds to work with the toolchain.
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