Comments (2)
Oh, so that issue only shows up for those Kintex parts. Do smaller kintex parts work?
Yes, only for kc705 and hpcstore/sitlinv-k420t. Other parts work including qmtech-xc7k325t.
Comparing xilinx_kc705.py and qmtech-xc7k325t.py litex targets, I found that the main difference comes down to the use of PHYPadsReducer. After updating xilinx_kc705 to use [0,1] modules (and no larger subset), yosys no longer infers unsupported LUTRAM primitives.
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
from litedram.common import PHYPadsReducer
- self.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
+ self.ddrphy = s7ddrphy.K7DDRPHY(
+ #PHYPadsReducer(platform.request("ddram"), [0, 1, 2, 3, 4, 5, 6, 7]),
+ PHYPadsReducer(platform.request("ddram"), [0, 1]),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT8JTF12864(sys_clk_freq, "1:4"),
l2_cache_size = kwargs.get("l2_size", 8192)
The obvious workaround is using yosys 0.17.
Yes, this much is clear. However, I am interested in getting more primitives supported. Do you mind opening issues tab for prjxray or prjxray-db forks for tracking unsupported primitives?
from demo-projects.
Oh, so that issue only shows up for those Kintex parts. Do smaller kintex parts work?
I really need to set up a CI.
The obvious workaround is using yosys 0.17.
from demo-projects.
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