nandland / nandland

All code found on nandland is here. underconstruction.gif

Contains all project code found on www.nandland.com

nandland's Issues

Getting compile error on Binary_To_BCD_Double_Dabble in VDHL

In the state"s_ADD" am getting compile error which says "expression is not constant" for the expression v_BCD_Digit := unsigned(r_BCD(v_Upper downto v_Lower));. Any ides how to solve this problem?

`when s_ADD =>
v_Upper := r_Digit_Index4 + 3;
v_Lower := r_Digit_Index4;
v_BCD_Digit := unsigned(r_BCD(v_Upper downto v_Lower));

      if v_BCD_Digit > 4 then
        v_BCD_Digit := v_BCD_Digit + 3;
      end if;

      r_BCD(v_Upper downto v_Lower) <= std_logic_vector(v_BCD_Digit);
      r_SM_Main <= s_CHECK_DIGIT_INDEX;`

Bug in Binary to BCD

I was going through the Binary to BCD VHDl code and tried synthezing it on Quartus. However there was an error in the statement

      v_BCD_Digit := unsigned(r_BCD(v_Upper downto v_Lower));

where a constant is expected.

Joseph

UART_RX and TX reset signals

In your online videos the RX and TX modules do not have reset lines. Your demo projects work fine

The code in this repo have !reset lines as inputs. If I use those modules to work through the demos they dont work. The reset dangles.

Took me some time to work out I had to hard wire these resets to 1.

It would also be nice to have the source of the loop back demo in the repo.

tooling setup - project 3

Presently can't seem to configure arachne-pnr or yosys to take in the shown .sdc file. With man arachne-pnr and man yosys, the former has the -p flag to take in the .pcf file, and while the latter has the -m and -f flags; these do not seem to apply in the case of configuring clocking. (Environment has these three packages installed: arachne-pnr, yosys and fpga-icestorm)
In the case of Combinational Logic Design, the following does flash a bitstream: (thanks to Russell for sharing: https://youtu.be/P-9WCFi0p-0)

build.sh:

#!/bin/bash
yosys -p "read_verilog *.v; synth_ice40 -blif file.blif"
arachne-pnr -d 1k -p Go_Board_Constraints.pcf -P vq100 -o file.hex file.blif

flash.sh:

#!/bin/bash
icepack file.hex file.bin
iceprog file.bin

I've used the above scripts for project 1 and 2 with success. Project 3 may also appear to flash successfully until one examines the build Statistics of synthesis. While the line place_constraints... is in yosys' output, having Number of memories: 0 and DFF 0 shows the lack of any clock configuration(s) reaching the resultant output file to flash. I don't know how to change that - presently.

Has Sequential Logic functionality gotten to a point of implementation in either of these tools and subsequently their documentation to be enabled? Thanks to the package author(s) for what we have thusfar with the above functionality. Looking forward to continuing pursuit of further FPGA programming and project development. Regardless of development status, have found nextpnr on github and may look into using that as an option to explore going forward.

Timing bug in VGA

Hi Russell,

I debug it modelsim and found there is a timing bug in your VHDL VGA implementation.

In VGA_Sync_Porch, you make

• o_HSync, o_VSync delay two clock cycles relative to i_HSync and i_VSync
• o_Red_Video, o_Blu_Video and o_Grn_Video delay two clock cycles relative to i_Red_Video, i_Blu_Video and i_Grn_Video

But in VGA_Test_Patterns_Top, you wire

• i_Red_Video, i_Blu_Video and i_Grn_Video to w_Red_Video_TP, w_Blu_Video_TP and w_Grn_Video_TP from test patern
• but wire i_HSync and i_VSync to w_HSync_VGA and w_VSync_VGA from VGA sync pulse

I can see that w_Red_Video_TP, w_Blu_Video_TP and w_Grn_Video_TP delay two clock cycle relative to w_HSync_VGA and w_VSync_VGA.

Overall, o_VGA_Hsync and o_VGA_VSync is two clock cycle ahead of o_VGA_Red, o_VGA_Blu and o_VGA_Grn

To compensate the mess, you manually increase horizontal front porch and back porch by 2 pixel clocks, eg the standard front porch 16 pixel clock to your 18 pixel clock and the standard back porch 48 pixel clock to your 50 pixel clock

(See https://www.nandland.com/goboard/vga-introduction-test-patterns.html)

I fixed it for you by removing redundant two clock cycle delays (https://github.com/rickyzhang82/Go-Board-FPGA-Projects/blob/master/VGA/src/VGA_Sync_Porch.vhd#L120-L122) and set the standard front porch and back porch (https://github.com/rickyzhang82/Go-Board-FPGA-Projects/blob/master/VGA/src/VGA_Sync_Porch.vhd#L48-L49)

You can see the differences from the attached photos in black and white bars.

Your original version shows misaligned line in the front (on the left):

while mine show aligned line in the the front:

Time type error

Hey Russell,

in line 82 at the UART_TB.vhdl there is an error concering the time type. Probably because you can't convert a time into a time. Getting rid of the "ns" at the resolves it.

Thanks for the great tutorials!

Keep it up
Michael

Timing issue in UART_RX

In UART_RX.v, r_Clock_Count is synched to the middle of the incoming bits. Hence, in case RX_STOP_BIT we should wait only CLKS_PER_BIT/2-1 cycles for the end of the stop bit, not the current CLKS_PER_BIT-1.

I found that making this change fixed occasional freezes at low baud rate (9600).

Thank you for the great work in this series.

Instructions for building with icestorm?

After waiting a few days without a response from Lattice for a free license, I decided to move forward without Icecube2 (Linux is more convenient for me, anyway!)

I've installed icestorm and the related tools, and got the early exercises working:

yosys -p "read_verilog $^; synth_ice40 -json $@"
nextpnr-ice40 --lp1k --pcf go.pcf --package vq100 --asc $@ --json $<
icepack $< $@
iceprog $<

These seem to work, but I'm worried that there might be something subtle I'm missing (I'm new FPGAs and working through the book!).

Also, it appears that this makes a 12MHz clock (from the output of nextpnr), but I can't figure out how to use the .sdc files from the book, or where else I could do create_clock.

Any help would be much appreciated!