mipt-ilab / mipt-mips Goto Github PK

Currently if a header file is changes, no rebuild is performed by Make. There is a way how to trace dependencies from headers automatically: http://stackoverflow.com/questions/2394609/makefile-header-dependencies

AMB: every Makefile contains correct dependencies

You have to introduce DataBypass class which will allow to perform bypassing between different pipe stages. The implementation should be close to scoreboard (producers mark registers as bypassible, consumers check if their registers are bypassible).

AMB: DataBypass class is fully connected to MIPT-MIPS and enabled in testing.

Looks like a nice manual: http://stackoverflow.com/questions/35998856/how-can-i-use-google-test-with-my-project-that-builds-via-autotools

Historically assignments were about creation a tool and a unit test for it. However, now we can put all unit tests to the single unit, so they can be by single command.

AMB: Make MIPT-MIPS fully buildable with Windows-Ubuntu. Manual to install required dependencies is published on Wiki.

Currently we use uint64 for accounting cycles. We may add better types with operator overloading, so some operations would be prohibited (like adding cycles to cycles).

Valid operations:

Cycle + Latency => Cycle
Cycle - Latency => Cycle
Cycle - Cycle => Latency
Cycle (compare) Cycle => bool
Latency + Latency => Latency
Latency - Latency => Latency
Latency / int => latency
Latency * int => Latency
int * Latency => Latency
Cycle % int => int

Examples of invalid operations:

Cycle * (anything)
Cycle / (anything)
Latency - Cycle

Both types should support literals.

Currently we define CXXFLAGS in each Makefile. The object is to add one Makefile in $TRUNK to keep all the options.

AMB: root Makefile is added, all other Makefiles include it,

AMB: all common infrastructure is moved to the base class with zero impact on MIPT-MIPS accuracy.

Checklist

• Add dedicated unit tests for CacheTagArray
• Convert miss_rate_sim to LRU policy test
• Convert portstest.cpp to ports test
• Add semantic tests to ports test

There are two options at the moment: either all units do dump or none of them. The idea is to provide string name to each unit ("bp", "datacache" etc.) and enable their dump from command line:
./mipt-mips -units_log bp,datacache,fetch.

To implement this, Module class (#357) should be coupled with existing Log class, and Valuestd::string object.

Currently factorial fails on instruction 62:

./perf_sim -b ../tests/samples/factorial.out -n 100 -d -f

jr $ra
perf_sim: ../func_sim/func_memory/func_memory.cpp:79: uint64 FuncMemory::read(uint64, short unsigned int) const: Assertion `check( addr)' failed.

The problem is that jal istruction does not perform writeback to $ra register.

With BPU enabled, we may re-arrange clocking of stages in natural FDEMW order. After completion, you should provide IPC drift numbers.

In func_instr:

$ make
g++-6 -std=c++14 -Wall -Wextra -Werror -O3 -c ../../func_sim/func_memory/func_memory.cpp -I ../../
g++-6 -std=c++14 -Wall -Wextra -Werror -O3 -MM -o  func_memory.d ../../func_sim/func_memory/func_memory.cpp -I ../../
g++-6 -std=c++14 -Wall -Wextra -Werror -O3 -c ../../func_sim/elf_parser/elf_parser.cpp -I ../../
g++-6 -std=c++14 -Wall -Wextra -Werror -O3 -MM -o  elf_parser.d ../../func_sim/elf_parser/elf_parser.cpp -I ../../
g++-6 -std=c++14 -Wall -Wextra -Werror -O3 -c disasm.cpp -I ../../
disasm.cpp: In function 'int main(int, char**)':
disasm.cpp:30:47: error: cannot convert 'std::__cxx11::string {aka std::__cxx11::basic_string<char>}' to 'const char*' for argument '1' to 'int strcmp(const char*, const char*)'
         if ( !strcmp( section[i].name, argv[2]))
                                               ^

In perf_sim:

 $ make
[g++-6] elf_parser.o
[g++-6] func_memory.o
[g++-6] func_instr.o
[g++-6] perf_sim.o
perf_sim.cpp:15:14: error: 'uint' does not name a type
 static const uint PORT_BW = 1;
              ^~~~

AMB: make MIPT-MIPS fully buildable with MSVS. Add a wiki manual if there are some tricks.

I've added MSVC command line build to AppVeyor with two noted

1. I have to use patched LibELF build as original source contains a small bug
2. MIPS binutils are built only by MinGW — it is OK as we use only binaries

Besides, everything is OK to create *.sln and *.vcxproj files (NMake is very, very bad)

The object is to re-write that code using reverse_iterators:

0349d46

AMB: Boost is added to build system. Parsing of arguments is performed with boost.

Currently ElfParser and Disassembler do the same job of printin contents of MIPS binary file. The tools should be merged to one tool which prints both data and disassembled instructions.

Recently PVS-Studio developers provided a free service to use their static analyzer tool. We would like to use in our project.

Information: http://www.viva64.com/ru/b/0457/

AMB: PVS Studio support enabled in MIPT-MIPS. Something is found :-)

There are two options at the moment: either all units do dump or none of them. The idea is to provide string name to each unit ("bp", "datacache" etc.) and enable their dump from command line. It should be implemented by combination of Log and Config classes.

Currently deadlocks are not handled, simulator gets into an infinite loop. There should be a very simple handler — if there are no writebacks in previous 1000 cycles, error message is printed.

The goal is to integrate testing to GitHub, so some unit tests will be run for every pull request.

I personally prefer to enable as much C++ warnings as it is possible with -Wall -Wextra -Werror flags. Can someone please enable these flag and fix warnings appeared?

AMB: These flags are enabled in all Makefiles, all builds pass.

We have a cache model implemented, but it is not connected to PerfSim.

AMB: Data Cache Unit is implemented and performance studies are made on memory stress trace.

We have a cache model implemented, but it is not connected to PerfSim.

AMB: Instruction Cache Unit is implemented and performance studies are made on instruction stress trace.

Currently to add a new option one needs to add it to config.h and config.cpp. The goal is to initialize any value with single code line.

AMB: GZipped traces can opened just as common ones

AMB: GoogleTest library is deleted from MIPT-MIPS repository. Manual how to install GoogleTest is uploaded to Wiki.

A command line option should select what simulator has to be run

Currently uint64 is used to represent address. However, we have to use Addr type instead.

We do not test correctness of instruction execution, this functionality has to be implemented.

Currently mem_trans.s is designed to test Data Cache Unit, but we might want to test Instruction Cache Unit. So, the new trace should contain non-memory instructions.

MIPS ISA defines LO and HI registers with implicit access by following instructions:

• mult
• multu
• div
• divu
• mfhi
• mthi
• mflo
• mtlo

MIPS restricts LO and HI usage to simplify dependency tracking (thus you have to track them as single register)

A computed result written to the HI/LO pair by DIV, DIVU,MULT, or MULTU must be read by MFHI or MFLO before a new result can be written into either HI or LO. If an MTHI instruction is executed following one of these arithmetic instructions, but before an MFLO or MFHI instruction, the contents of LO are UNPREDICTABLE. The following example shows this illegal situation:

 MUL       r2,r4   # start operation that will eventually write to HI,LO
 ...               # code not containing mfhi or mflo
 MTHI      r6
 ...               # code not containing mflo
                   # this mflo would get an UNPREDICTABLE value
 MFLO      r3

Example to reproduce:

$ ./perf_sim -b ../tests/samples/factorial.out -n 1300 -d
wb      cycle 147:bubble
decode  cycle 147:bubble
fetch   cycle 147:bubble
execute cycle 147:bubble
memory  cycle 147:mflo $t3, $zero, $zero	 [ $t3 = 0x0]
Executed instructions: 69

wb      cycle 148:mflo $t3, $zero, $zero	 [ $t3 = 0x0]
****************************
Mismatch: 
Checker output: mflo $t3, $zero, $zero	 [ $t3 = 0x1]
PerfSim output: mflo $t3, $zero, $zero	 [ $t3 = 0x0]

In MDSP, we used to have Log class which allows to quickly enable or disable logging. We want to port it from MDSP to MIPT-MIPS and remove all std::cout usage.

Currently we run PerfSim and FuncSim independently and then compare logs. However, if FuncSim was started inside PerfSim, we may get results a little bit simpler and faster.

AMB: mem_trace.s size is reduced, so we have "C++" as main language in GitHub

We have testing only for addu, addi, j. All the instructions must be covered.

Currently no testing for Branch Prediction is made. We have to add the trace with huge amount of random branches.

The candidate was a bubble sort, but unfortunately, it is has low sensitivity to branch prediction.

AMB: Trace is implemented and shows sensitivity to BP mode.

AMB: GoogleTest library in MIPT-MIPS is bumped to new version, testing works fine.

After fixing #73 I get

$ ./perf_sim -b ../tests/samples/factorial.out -n 1300 -d
wb      cycle 147:bubble
decode  cycle 147:bubble
fetch   cycle 147:bubble
execute cycle 147:bubble
memory  cycle 147:mflo $t3, $zero, $zero	 [ $t3 = 0x0]
Executed instructions: 69

wb      cycle 148:mflo $t3, $zero, $zero	 [ $t3 = 0x0]
****************************
Mismatch: 
Checker output: mflo $t3, $zero, $zero	 [ $t3 = 0x1]
PerfSim output: mflo $t3, $zero, $zero	 [ $t3 = 0x0]

For the most of cases, execution of several (>10) sll $0, $0, 0x0 instructions means that program is executed incorrectly. We need to have an automized detector of such instructions in FuncSim to stop simulation if such sequence is detected.

Problem with Factorial program.

To reproduce:

mipt-mips/tests/samples$ make build_all
mipt-mips/perf_sim$./perf_sim ../tests/samples/factorial.out 100 -d

Error message:

Executed instructions: 5

    fetch	cycle 15:  0x23bdfff4
    decode	cycle 15:  bubble
    execute	cycle 15:  or $t0, $v0, $zero	 [ $t0 = 0x4]
    memory	cycle 15:  syscall
ERROR: Writing to valid register!

AMB: C++11 is enabled as default standard in MIPT-MIPS. C++03 types are removed from types.h

Currently MIPS ISA is stored in C-style static array. With C++11 we may initialize something like std::list or std::unordered_map during compile-time.

MIPT-MIPS cannot model self-modifying code at the moment. However, at least we have to add some tests for that.
AMB: trace is added and demonstrates different behavior on Functional and Performance simulation

The trace goes to deadlock.

How to reproduce:

./perf_sim ../tests/samples/memtrace_based.out 100 -d

AMB: build manuals for FuncSim and PerfSim are available on Wiki.