Fork mem_trans.s to generate ICU stress test about mipt-mips

[pavelkryukov]

@ivan23kor

That is a very simple task although important one. You have to replace all memory instructions to non-memory instructions in copy of mem_trans.s (would be code_trans.s).
MIPS instructions https://github.com/MIPT-ILab/mipt-mips/wiki/MIPS-Instruction-Set. However, our simulator does not support all of them, here is the list of all supported instructions: https://github.com/MIPT-ILab/mipt-mips/blob/master/func_sim/func_instr/func_instr.cpp

[pavelkryukov]

@ivan23kor Please share your progress on this.

[ivan23kor]

Sorry to tell you, I have a lack of time so I won't commit to the repository.

…

On Mon, Feb 27, 2017 at 4:38 PM, Pavel Kryukov ***@***.***> wrote: @ivan23kor <https://github.com/ivan23kor> Please share your progress on this. — You are receiving this because you were mentioned. Reply to this email directly, view it on GitHub <#35 (comment)>, or mute the thread <https://github.com/notifications/unsubscribe-auth/ANwcNDQe5FVYY0VcrVPB2zBITkR1MW1Dks5rgtHwgaJpZM4L1Z_2> .

-- Best, Ivan

[gkorepanov]

I'm sorry for a couple of silly questions:

1. I'm wondering what are the DCU and ICU?
2. find haven't gave me any file named mem_trans.s in our repo. Am I missing something?

[igorsmir-ilab]

Hello,

1. DCU stands for "Data Cache Unit", while ICU means "Instruction Cache Unit". They are also called L1D and L1I, where L1 means "level 1" cache. You may find processor terminology e.g. in section 1.2 of Intel cheatsheet.
2. I believe @pavelkryukov meant our memory test, which is currently located under tests/samples and called memtrace_based.s, not mem_trans.s.

[pavelkryukov]

Yep, sure I meant memtrace_based.s

[gkorepanov]

I'm really grateful for your explanations and references. I believe it will help me to proceed.

[pavelkryukov]

@gkorepanov Any progress?

[pavelkryukov]

Kamino closed and cloned this issue to MIPT-ILab/mips-traces