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cnn_ocl_fpga

ConvNet project using OpenCL on Xilinx FPGA

cnn_open

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

convnn_fpga_accelerator

convolution_network_on_fpga

CNN acceleration on virtex-7 FPGA with verilog HDL

cs-notes

:books: 技术面试必备基础知识、Leetcode 题解、后端面试、Java 面试、春招、秋招、操作系统、计算机网络、系统设计

cudnn

dcgan-fpga

Verilog implementation of the generator of DCGAN on FPGA

deep-compression-alexnet

Deep Compression on AlexNet

deep-convolutional-network-on-fpga

a simplified version of LeNet5

deep-learning-fpga

Source code for Final Year Thesis on implementations of deep learning accelerators on FPGAs.

deepcompression-caffe

Caffe for Deep Compression

deploying_cnn_on_fpga_using_opencl

Squeezenet V1.1 on Cyclone V SoC-FPGA at 450ms/image, 20x faster than ARM A9 processor alone. A project for 2017 Innovate FPGA design contest.

dnnweaver2

Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.

ece395a

Neural net implementation on an FPGA.

ece5775-final

Voice Recognition using FPGA-Based Neural Networks

em070_new-fpga-family-for-cnn-architectures-high-speed-soft-neuron-design

Who doesn’t dream of a new FPGA family that can provide embedded hard neurons in its silicon architecture fabric instead of the conventional DSP and multiplier blocks? The optimized hard neuron design will allow all the software and hardware designers to create or test different deep learning network architectures, especially the convolutional neural networks (CNN), more easily and faster in comparing to any previous FPGA family in the market nowadays. The revolutionary idea about this project is to open the gate of creativity for a precise-tailored new generation of FPGA families that can solve the problems of wasting logic resources and/or unneeded buses width as in the conventional DSP blocks nowadays. The project focusing on the anchor point of the any deep learning architecture, which is to design an optimized high-speed neuron block which should replace the conventional DSP blocks to avoid the drawbacks that designers face while trying to fit the CNN architecture design to it. The design of the proposed neuron also takes the parallelism operation concept as it’s primary keystone, beside the minimization of logic elements usage to construct the proposed neuron cell. The targeted neuron design resource usage is not to exceeds 500 ALM and the expected maximum operating frequency of 834.03 MHz for each neuron. In this project, ultra-fast, adaptive, and parallel modules are designed as soft blocks using VHDL code such as parallel Multipliers-Accumulators (MACs), RELU activation function that will contribute to open a new horizon for all the FPGA designers to build their own Convolutional Neural Networks (CNN). We couldn’t stop imagining INTEL ALTERA to lead the market by converting the proposed designed CNN block and to be a part of their new FPGA architecture fabrics in a separated new Logic Family so soon. The users of such proposed CNN blocks will be amazed from the high-speed operation per seconds that it can provide to them while they are trying to design their own CNN architectures. For instance, and according to the first coding trial, the initial speed of just one MAC unit can reach 3.5 Giga Operations per Second (GOPS) and has the ability to multiply up to 4 different inputs beside a common weight value, which will lead to a revolution in the FPGA capabilities for adopting the era of deep learning algorithms especially if we take in our consideration that also the blocks can work in parallel mode which can lead to increasing the data throughput of the proposed project to about 16 Tera Operations per Second (TOPS). Finally, we believe that this proposed CNN block for FPGA is just the first step that will leave no areas for competitions with the conventional CPUs and GPUs due to the massive speed that it can provide and its flexible scalability that it can be achieved from the parallelism concept of operation of such FPGA-based CNN blocks.

embedded-neural-network

collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning

face-detection-on-fpga

This a complete and fully working Viola-Jones face detection algorithm described in VHDL and verified on the DE2-115 FPGA board.

facedetect-fpga

feathercnn

FeatherCNN is a high performance inference engine for convolutional neural networks.

finn

Fast, Scalable Quantized Neural Network Inference on FPGAs

fpga-accelerator-for-aes-lenet-vgg16

FPGA/AES/LeNet/VGG16

fpga-cnn

FPGA implementation of Cellular Neural Network (CNN)

fpga-cnn-1

This repo is for ECE44x (Fall2015-Spring2016)

fpga-dcnn-accelerator

基于HLS的高效深度卷积神经网络FPGA实现方法

fpga-edge_detect

Nexys 4 DDR Artix-7

fpga-fast

FPGA FAST image feature detector implementation in VHDL

fpga-hash-table

Simple hash table on Verilog (SystemVerilog)

fpga-mnist

Hand written number classification done in hardware (De1-SoC board) using neural networks

fpga-nn

NN on FPGA