Name: Mike Thompson
Type: User
Company: @openhwgroup
Bio: Functional verification of RTL for ASICs and FPGAs. Sole Proprietor at Covrado and Director of Engineering, Verification Task Group at the OpenHW Group.
Location: Ottawa, Ontario, Canada
Blog: http://www.openhwgroup.org
Mike Thompson's Projects
Advanced Verification Methodologies for RISC-V and related IP
A bare metal programming guide (ARM microcontrollers)
CORE-V Family of RISC-V Cores
RISC-V Random Instruction Stream Generator
This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
Eclipse/FreeRTOS/core-v-mcu example program
This is the CORE-V MCU DevKit project, hosting the open-source artifacts for the CORE-V MCU Development Kit.
CORE-V MCU UVM Environment and Test Bench
Functional verification project for the CORE-V family of RISC-V cores.
RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
Experiment repo to facilitate existing core-v-docs documents to reStructuredText and a readthedocs flow.
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
βοΈPort of RISCOF to demonstrate the CV32E40P Processor's RISC-V ISA compatibility.
4 stage, in-order, secure RISC-V core based on the CV32E40P
4 stage, in-order, compute RISC-V core based on the CV32E40P
CV32E40X Design-Verification environment
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
Configurable RISC-V Processor
Documentation for RISC-V Spike
Experimenting with DVplan reviews
To deliver production-ready platforms for the development, operation, and management of edge native applications deployed to heterogeneous environments where computational power and data storage are physically distributed wherever they are needed.
A minimal operating system (2K LOC) on QEMU and a RISC-V board
Instruction Set Generator initially contributed by Futurewei
This is a repository where all GitHub For Dummies readers can add a link to their GitHub profile! The purpose of this repo is to experiment with Workflows.
Documentation for the OpenHW Group's set of CORE-V RISC-V cores