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advanced-riscv-verification-methodologies

Advanced Verification Methodologies for RISC-V and related IP

bare-metal-programming-guide

A bare metal programming guide (ARM microcontrollers)

core-v-cores

CORE-V Family of RISC-V Cores

core-v-isg

RISC-V Random Instruction Stream Generator

core-v-mcu

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

core-v-mcu-cli-test

Eclipse/FreeRTOS/core-v-mcu example program

core-v-mcu-devkit

This is the CORE-V MCU DevKit project, hosting the open-source artifacts for the CORE-V MCU Development Kit.

core-v-mcu-uvm

CORE-V MCU UVM Environment and Test Bench

core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

core-v-xif

RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions

core-v_verif_docs

Experiment repo to facilitate existing core-v-docs documents to reStructuredText and a readthedocs flow.

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

cv32e40p-riscof

✔️Port of RISCOF to demonstrate the CV32E40P Processor's RISC-V ISA compatibility.

cv32e40s

4 stage, in-order, secure RISC-V core based on the CV32E40P

cv32e40x

4 stage, in-order, compute RISC-V core based on the CV32E40P

cv32e40x-dv

CV32E40X Design-Verification environment

cva5-accelerators

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

cve2

Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

cvw

Configurable RISC-V Processor

documentation_spike

Documentation for RISC-V Spike

dvplan_reviewer

Experimenting with DVplan reviews

edgenative.eclipse.org

To deliver production-ready platforms for the development, operation, and management of edge native applications deployed to heterogeneous environments where computational power and data storage are physically distributed wherever they are needed.

egos-2000

A minimal operating system (2K LOC) on QEMU and a RISC-V board

experimental-repo

force-riscv

Instruction Set Generator initially contributed by Futurewei

githubfordummiesreaders

This is a repository where all GitHub For Dummies readers can add a link to their GitHub profile! The purpose of this repo is to experiment with Workflows.

marketing

programs

Documentation for the OpenHW Group's set of CORE-V RISC-V cores

pulp_soc