merledu / buraq_mini

This repository contains the 5 stage pipelined CPU implemented on the RISC-V ISA and Chisel hardware construction language (HDL)

Buraq-Mini: An In-Order Fully Bypassed RISC-V Core

Buraq-Mini is a 5 stage pipelined processor which is made in Chisel from scratch and is used inside the "Ibtida SoC" which is selected for the first open-source ASIC tapeout in the Google + Efabless Open MPW Shuttle program.


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Note:

This repository standalone does not build. Check the decoupled-interface branch for more details on how to build the repository.

buraq_mini's Issues

CSRs for the core need to be implemented

Test failing of I-type instructions

The i-type extension is currently not working with the master branch. @sajjadahmed677 please resolve this issue

UART and GPIO functionality

The project is lacking the UART and GPIO functionality.

Have to manually change the file path for program file

Right now we have to manually provide the path of program file that is to be loaded in the instruction memory. Since we are working on multiple platforms (Linux, Mac) each user has to provide the location of the file manually. Let's make a functionality of dynamic path loading of program file, which finds the correct path of the program file itself from the user's environment.

Fetch Unit Needs Modification

Current fetch unit of Buraq_Mini is aligned with async memory model which should be aligned with sync memory model and should have support for misaligned fetch.

M Extension

The Buraq-mini compute must have an M-extension for support of multiply and divide instructions.

C for loop with arrays not working

Running the risc-v benchmark tests were failing while using arrays of large numbers. The compiler creates an assembly which uses Lui instruction that is yet to be implemented in the core.

The README.md file needs to be updated

Store Byte/ Store Half Word issues

store byte and store half word instructions needs to be properly handled along with OpenRam memory model and tilelink. current issue is read modify write operation, when an instruction of sb or sh is encountered. it is dependent upon OpenRam memory model, whether it will be a read modify write operation(which takes multiple cycles) or writing particular byte into the memory.

LSU module needs modification.

Right now there is no check for detecting misaligned load store operations so, Load store unit needs to be modified for misaligned load store operations. it should also be aligned with the OpenRam memory model.

Loading Instruction Memory through UART

@hadirkhan10 what if? we read an instruction file in UART test bench for loading instruction memory, rather then arranging instructions in an array inside UART test bench. it will save the time of arranging instructions in an array.

flaw in JALR forwading logic

JALR forwarding logic gets true even when there are independent instructions.

Need to place the pipeline registers into their own relevant module

We can move the IF/ID pipeline registers in the Fetch, ID/EX into the Decode, EX/MEM into the Execute and MEM/WB into the Memory stage.

Please add a LICENSE file

It is currently missing.

OpenRam memory model needs to be implemented

Right now Buraq_Mini has async memory model which is needed to be replaced with OpenRam memory model.

Long array isn't working.

Array of more than 14 elements is not working while using BURQ generated assembly. reason is AUIPC, LB and SB instructions are not implemented.

Update the core interface to match with TileLink implementation

The previous TileLink implementation has been removed from the repository and is upgraded and moved into it's own repository here so the core is not running and producing errors. Need to create an interface for TileLink according to the new implementation.

Tilelink interfaces needs to be implemented in core

for connecting tilelink with core module two interfaces are required one fore fetch unit for connecting ICCM and another one for memory stage for connecting DCCM.

flaw in stalling logic(Hazard detection unit)

An unwanted stall occurs in when there are multiple load instructions.