Comments (2)
JALR instruction only have RD and RS1 fields along with an immediate. and forwarding for RS1 is done by comparing RD of execute, Memory and Writeback stage with RS1 of Decode stage, but our forwarding logic is for both jump and branch so there is an additional field of RS2( of Decode stage) in comparison.
forwarding logic with bug.
// ALU Hazard
when( io.ID_EX_REGRD =/= "b00000".U && io.ID_EX_MEMRD =/= 1.U && (io.ID_EX_REGRD === io.rs1_sel)){
io.forward_rs1 := "b0110".U
}
// EX/MEM Hazard
when(io.EX_MEM_REGRD =/= "b00000".U && io.EX_MEM_MEMRD =/= 1.U &&
~((io.ID_EX_REGRD =/= "b00000".U) && (io.ID_EX_REGRD === io.rs1_sel)) &&
(io.EX_MEM_REGRD === io.rs1_sel)) {
io.forward_rs1 := "b0111".U
}
.elsewhen( io.EX_MEM_REGRD =/= "b00000".U && io.EX_MEM_MEMRD === 1.U &&
~((io.ID_EX_REGRD =/= "b00000".U) && (io.ID_EX_REGRD === io.rs1_sel)) &&
(io.EX_MEM_REGRD === io.rs1_sel)) {
// FOR Load instructions
io.forward_rs1 := "b1001".U
}
// MEM/WB Hazard
when( io.MEM_WB_REGRD =/= "b00000".U && io.MEM_WB_MEMRD =/= 1.U &&
// IF NOT ALU HAZARD
~((io.ID_EX_REGRD =/= "b00000".U) && (io.ID_EX_REGRD === io.rs1_sel)) &&
// IF NOT EX/MEM HAZARD
~((io.EX_MEM_REGRD =/= "b00000".U) && (io.EX_MEM_REGRD === io.rs1_sel)) &&
(io.MEM_WB_REGRD === io.rs1_sel)) {
io.forward_rs1 := "b1000".U
}
.elsewhen(io.MEM_WB_REGRD =/= "b00000".U && io.MEM_WB_MEMRD === 1.U &&
// IF NOT ALU HAZARD
~((io.ID_EX_REGRD =/= "b00000".U) && (io.ID_EX_REGRD === io.rs1_sel)) &&
// IF NOT EX/MEM HAZARD
~((io.EX_MEM_REGRD =/= "b00000".U) && (io.EX_MEM_REGRD === io.rs1_sel)) &&
(io.MEM_WB_REGRD === io.rs1_sel)) {
// FOR Load instructions
io.forward_rs1 := "b1010".U
}
in previous logic there was no check over the type of instruction so whenever these fields get same value the condition for forwarding gets true and there will be an unwanted jump address. so now we have put a check on instruction type whether the instruction is of Register instruction or not.
current forwarding logic.
// ALU Hazard
when(io.execute_regwrite === 1.U && io.ID_EX_REGRD =/= "b00000".U && io.ID_EX_MEMRD =/= 1.U && (io.ID_EX_REGRD === io.rs1_sel)){
io.forward_rs1 := "b0110".U
}
// EX/MEM Hazard
when(io.mem_regwrite === 1.U && io.EX_MEM_REGRD =/= "b00000".U && io.EX_MEM_MEMRD =/= 1.U &&
~((io.ID_EX_REGRD =/= "b00000".U) && (io.ID_EX_REGRD === io.rs1_sel)) &&
(io.EX_MEM_REGRD === io.rs1_sel)) {
io.forward_rs1 := "b0111".U
}
.elsewhen(io.mem_regwrite === 1.U && io.EX_MEM_REGRD =/= "b00000".U && io.EX_MEM_MEMRD === 1.U &&
~((io.ID_EX_REGRD =/= "b00000".U) && (io.ID_EX_REGRD === io.rs1_sel)) &&
(io.EX_MEM_REGRD === io.rs1_sel)) {
// FOR Load instructions
io.forward_rs1 := "b1001".U
}
// MEM/WB Hazard
when(io.wb_regwrite === 1.U && io.MEM_WB_REGRD =/= "b00000".U && io.MEM_WB_MEMRD =/= 1.U &&
// IF NOT ALU HAZARD
~((io.ID_EX_REGRD =/= "b00000".U) && (io.ID_EX_REGRD === io.rs1_sel)) &&
// IF NOT EX/MEM HAZARD
~((io.EX_MEM_REGRD =/= "b00000".U) && (io.EX_MEM_REGRD === io.rs1_sel)) &&
(io.MEM_WB_REGRD === io.rs1_sel)) {
io.forward_rs1 := "b1000".U
}
.elsewhen(io.wb_regwrite === 1.U && io.MEM_WB_REGRD =/= "b00000".U && io.MEM_WB_MEMRD === 1.U &&
// IF NOT ALU HAZARD
~((io.ID_EX_REGRD =/= "b00000".U) && (io.ID_EX_REGRD === io.rs1_sel)) &&
// IF NOT EX/MEM HAZARD
~((io.EX_MEM_REGRD =/= "b00000".U) && (io.EX_MEM_REGRD === io.rs1_sel)) &&
(io.MEM_WB_REGRD === io.rs1_sel)) {
// FOR Load instructions
io.forward_rs1 := "b1010".U
}
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@sajjadahmed677 please resolve this issue and send a pull request
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