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"Mehmet Burak Aykenar" YouTube kanalında yayınlanan VHDL ve FPGA dersleri ile ilgili kodları içermektedir.

License: GNU General Public License v3.0

VHDL 96.32% Verilog 1.63% Tcl 1.88% C 0.15% MATLAB 0.03%

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apis_anatolia's Issues

AXI_ uart full software

Hello,

Thank you for your lessons they are very helpful for us, i just found out about them.
I was playing around with the axi uart full, I integrated it into my microblaze design and I would like to know if you have a little software that do the send stop read write functions.

I'm very new in the VHDL world (not even 6 discontinued months of experience) thus i can't help to figure out how to do software for a custom IP.

Kind regards.

Uart Receiver Modülü: stop bit tamamlanması beklenmiyor

VHDL ile FPGA programlama serisi ders 18'de uart alım yaparken stop bitinin tamalanmasını beklemeden, son stop bitinin tam ortasında rx_done_tick_o çıkışı 1 yapılıyor. Full-dublex kullanılıyorsa hiç bir problem yaratmayacaktır ancak half-dublex kullanıldığında bazı özel durumlarda veri transferinde hata oluşabilir.

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