llnl / msr-genie

Utility for fast and efficient queries about MSRs

msr-genie

MSR-Genie is a vendor-neutral tool for fast and efficient queries about model-specific registers (MSRs). The tool allows end users to query bi-directionally across MSR lists as well as processor families and models, and provides them with guidance on appropriate bitmasks.

GenieInterface is an interactive terminal-based interface to msr-genie. Upon execution of the program with ./GenieInterface, you will be greeted with a menu consisting of the following options.

(1) Debug
(2) Print MSR associated with df_dm (displayfamily_displaymodel)
(3) Print list of df_dm associated with MSR
(4) Get BitMask
(s) print list of supported df_dms
(c) clear screen
(h) help
(q) quit

Enter the corresponding number or letter for the option you wish to use and press enter to proceed. The menu will be reprinted after each selection.

GenieCLI is a command line interface to msr-genie. There are currently five (5) options for the CLI version.

1. Print list of supported df_dms: ./GenieCLI supported
2. Print MSR list for df_dm: ./GenieCLI [msr] [df_dm]
3. Print df_dm list for MSR: ./GenieCLI [df_dm] [msr]
4. Print bitmask: ./GenieCLI bitmask [df_dm] [msr]
5. Dump all DataStore values: ./GenieCLI debug
6. Create MSR allowlist template: ./GenieCLI allowlist

Building GenieCLI and GenieInterface

A makefile is provided for GenieCLI and GenieInterface. If your use case requires direct linkage to the header file, simply #include "Genie.h". There are no dependencies beyond a compatible C++ compiler.

MSR-Safe Allowlist Template Generator

MSR-Safe allowlist templates can be generated using the ./GenieCLI allowlist command. By default, it expects a directory called "safelist" within the msr-genie directory.

License

MSR-Genie is distributed under the terms of the MIT license.

See LICENSE and NOTICE for details.

SPDX-License-Identifier: MIT

LLNL-CODE-856773

References

LLNL collated this information from The Intel64 and IA-32 Architecture Software Developer's Manual Volume 4: Model-Specific Registers from [March 2023] document number [335592-079US]. While we took due care in its transcription, we might have made mistake or several. For the most recent an authoritative documentation, please consult the most recent version of Volume 4 at https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html Corrections and amplifications are most welcome.

Also note that processor firmware may choose to disallow access to particular MSRs. The fact that an MSR is listed here for a particular processor model does not guarantee that it will be accessible on your processor.

msr-genie's Issues

Generate tables from df_dm

The manual approach to generating cross-references survives in util/mapping.h.

std::vector<std::string> df_dm is a list of df_dms with their associated tables.

std::vector<std::string> tables is a list of tables with their associated df_dms.

Trying to update both when a new version of the Intel manual drops is proving to be excessively error-prone. Use one to generate the other. (The former is easier to read on the screen, the latter might be easier to update as new architectures are added.)

Add architecture code names

Add link to paper in README

https://dl.acm.org/doi/abs/10.1145/3624062.3624146

use getopt for argument parsing

Update based on Dec2023 release of Volume 4

My preliminary list:

Changes based on the Dec2023 edition of volume 4

Adds support for 06_AAH, 06_B7H, 06_BAH, 06_CFH.
Updates data for 06_6CH, 06_8EH, 06_8FH, 06_97H.
Adds tables 2-53, 2-54, 2-55.

2-20 -> 06_8FH 06_AAH 06_B7H 06_BAH 06_CFH
2-21 -> 06_8FH 06_AAH 06_B7H 06_BAH 06_CFH
2-25 -> 06_8FH 06_AAH 06_B7H 06_BAH 06_CFH
2-29 -> 06_8FH 06_AAH 06_B7H 06_BAH 06_CFH
2-35 -> 06_8FH 06_AAH 06_B7H 06_BAH 06_CFH
2-39 -> 06_8FH 06_AAH 06_B7H 06_BAH 06_CFH
2-41 -> 06_8EH
2-44 -> 06_B7H 06_BAH
2-45 -> 06_B7H 06_BAH
2-46 -> 06_B7H 06_BAH
2-49 -> 06_B7H 06_BAH
2-51 -> 06_6CH
2-52 -> 06_CFH
2-53 -> 06_AAH
2-54 -> 06_AAH
2-55 -> 06_AAH

06_6CH -> 2-51
06_8EH -> 2-41
06_8FH -> 2-20 2-21 2-25 2-29 2-35 2-39
06_AAH -> 2-20 2-21 2-25 2-29 2-35 2-39 2-53 2-54 2-55
06_B7H -> 2-20 2-21 2-25 2-29 2-35 2-39 2-44 2-45 2-46 2-49
06_BAH -> 2-20 2-21 2-25 2-29 2-35 2-39 2-44 2-45 2-46 2-49
06_CFH -> 2-20 2-21 2-25 2-29 2-35 2-39 2-52

Handle E-core and P-core

"MSRs at the following addresses are not supported in the 12th generation Intel Core processor E-core: 3F7H. MSRs at the following addresses are not supported in the 12th generation Intel Core processor E-core or P-core: 652H, 653H, 655H, 656H, DB0H, DB1H, DB2H, and D90H." (p. 2-331 v4)

"MSRs at the following addresses are not supported in the 12th and 13th generation Intel Core processor E-core: 30CH, 329H, 541H, and 657H. The MSR at address 657H is not supported in the 12th and 13th generation Intel Core processor P-core." (p 2-369)

"The MSRs listed in Table 2-47 are unique to the 12th and 13th generation Intel Core processor P-core. These MSRs are not supported on the processor E-core." (p 2-373)

"The MSRs listed in Table 2-48 are unique to the 12th and 13th generation Intel Core processor E-core. These MSRs are not supported on the processor P-core." (p 2-375)

"The MSRs listed in Table 2-54 are unique to the Intel Core Ultra 7 processor P-core. These MSRs are not supported on the processor E-core." (p 2-430)

"The MSRs listed in Table 2-48 are unique to the Intel Core Ultra 7 processor E-core. These MSRs are not supported on the processor P-core." (p 2-431)

I suspect we'll eventually need per-core-type msr-safe allowlists.