lerwys / bpm-sw-old-backup

Main repository for the BPM firmware and software

Welcome! 👋

• He is currently working at the Lawrence Berkeley National Laboratory

• LinkedIn : https://www.linkedin.com/in/lucas-maziero-russo-971b4727

• DockerHub : https://hub.docker.com/u/lerwys

bpm-sw-old-backup's Issues

[ddr3-sdram] phy_init_done never asserted

While perfomring simulation with DDR3 Xilinx Controller and DDR3 model the
"phy_init_done" signal from the controller is never asserted. Thus, causing
the simulation to hang forever

[fmc516] Select the appropriate delays to clock and data coming from ADC

There is a timing violation in that 1.4 acquisition window is not sufficient for IDDR, as reported
by timing analyzer.

Calibrate the delay from clock and data to match them.

[fmc-adc-data] Check registers in the datapath to ease timing

Consider removing it or improving this part of the code

Fix wrong xwb_fmc516 component declaration in custom_wishbone.vhd file

It's just what it is described in the title...

Replace IBUFGDS to IBUFDS

These are the same primitive, but the former instructs the mapper to use only global clock nets
(GCLK pins). BUT, as we know, we need to use non global clock nets in order to use BUFIO/BUFR primitives.

This possibly causes the error:

"ERROR:Place:1119 - The I/O components "adc_clk1_p_i" and "adc_clk1_n_i" are the
P- and N-sides of a differential I/O pair. The component "adc_clk1_p_i"
needs to be placed in a IOBM site and component "adc_clk1_n_i" in the
adjacent IOBS site within the same I/O tile. The following issue has been
detected:
Some of the logic associated with this structure is locked. This should cause
the rest of the logic to be locked. A problem was found at site BUFR_X0Y3
where we must place IOB adc_clk1_n_i in order to satisfy the relative
placement requirements of this logic. It is not legal to place this component
in this site. "

[fmc516] Fix reserved register fields

It should be Read-Only from the wishbone side and read as 0's!

[ethernet/ebone] Implement mux for ethernet packages?

Would it be viable to implement a mux in order to separate between etherbone packages and
other ones?

This is done for the white rabbit design. Specifically for the wr-core in which etherone packages
are redirect to etherbone and other messages to the rest of the FPGA fabric.

Study this possibility

[fmc516] Delay the falling edge data from the IDDR primitive

There is an issue regrading the sampling the data from the ISLA216 with the IDDR primitive. There needs to be an investigation to why this happens, but the solution is very simple...

change SPI three mode interface to miso/mosi/out_en

Implement ADC Reset and Reset Clk Div

There is a need to reset the ADCs and the clock output clock reset (for synchronization of
multiple ADC chips).

Also, they need to be software controllable.

[fmc516] Check ADC clock & MMCM values

Reimplement emb-sw fmc structures!

It is necessary to improve and make a more generic approach to the FMC boards

[wb_fmc130m_4ch] Add switching clock through MMCX connector

[fmc-adc-common] Fix BUFIO/BUFR/BUFG clk generation

Fix BUFIO/BUFR/BUFG clk generation in adc_clk.vhd entity, when 7SERIES FPGAs are selected

[pcie-core] Fix missing signal

We should always test our designs before committing it!

/home/lerwys/Repos/bpm-sw-test-pcie/hdl/top/pcie/top_ml605.vhd" Line 183: Formal port/generic <rst_act_low> is not declared in <bpm_pcie_ml605>

Insert CLOCK_DEDICATED_ROUTE=FALSE constraint to .ucf

"The CLOCK_DEDICATED_ROUTE=FALSE workaround is typically for source clocks which are not assigned to global clock input pins -- a completely different problem."

This could be the issue related to driving clock buffers from non GCLK pins.

[all] Unify SDB descriptors.

Add them to wishbone_pkg.vhd in general cores?

[FMC516] Check SPI communication

Especially with SPI 3-wire mode

Make wb_stream more generic

It would be better if the wishbone streaming interface could be more generic,
allowing data sizes of 16, 32, 64 or 128 bits wide. Moreover, the xwb_source and
xwb_sink modules wouls have to be modified.

[dsp-devel][fmc516] ADC Data appears to be off by one cycle

The ADC data channels 1 and 2 seems to be 1 clock out of sync with data channels 0 and 3.

[fmc516] Implement synchronization between all data chains with a single clock domain

The default behavior of the module is to clock the data with 2 clocks. In this way,
we have to sync the data of all 4 data chains to a single clock. By default, the first used clock will be used for this.

[fmc516] fix multiple MMCM primitives in adc_clock.vhd

[wb_acq_core] Add multiple "simultaneous" acquisition paths

There is a need to have multiple acquisition paths acquiring data simultaneous,
in a multiplexed way.

This is the traditional use case for our case, in that 1 AFC handles 2 BPMs signals.
So, at least we must decouple the acquisition paths from the 2 different BPMs

[fmc516] Implement automatic idelay selection

It is necessary o module to implement automatic delay calibration, as it is not pratical nor
robust to manually input them.

[soon-to-be fmc-port] Add g_with_bufio and g_with_bufr

This will allow selecting if we want the incoming clock to be routed to BUFIO and/or BUFR primitive. This effectively will clock an IDDR primitive with BUFIO and local FPGA logic with BUFR. Later, all data will be synch'ed to a global reference clock.

Cauting is taken to ensure safe passage from one clock domain to another with Async FIFOs

[ebone] Add etherbone support

It would be nice and very useful to support etherbone core from ohwr repository (http://www.ohwr.org/projects/etherbone-core).

By doing this, "real " testing could be done easily and scripts could be set up for
executing them automatically.

[emb-sw] Consider moving the emb-sw folder to another git repository

Then this git repository could be reference as a sub-module in bpm-sw

[fmc-516] Clean wb_fmc516 delay interface

The interface between the register core and the var_loadable/variable delay register is very confusing. Fix it!

Reorganize the dbe_bpm_fmc516 top files

There is a mix in this folder, as this synthesis test is not under development yet!
I think the best way to correct this is to create the synth test in the wb-fmc516-devel branch
and leave it untouched in the other ones.

[ddr3-core] Implement a DDR3 core wrapper for Xilinx MIG

It is necessary a wishbone wrapper to Xilinx MIG generated core.

In this way, we can store the large ammounts of DSP data.

useful links:

http://www.xilinx.com/support/documentation/ip_documentation/mig/v3_92/ug406.pdf
http://www.xilinx.com/support/documentation/ip_documentation/ds186.pdf
http://www.ohwr.org/projects/ddr3-sp6-core/wiki

[fmc516-sw] Support for multiple fmc516 cores (and boards...)

Implement a generic structure to support multiple instances of the fmc516 core, for example.

A simple way would be to create a generic identification structure in which the drive functions would poll in order to determine the correct core (which SPI, I2C, etcc) core to act

[wb_acq_core] Cleanup core and implement missing features

It is necessary to cleanup the wb_acq_core and implement the missing features like
external data-driven triggered acquisitions