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Related Issues (20)
- [fmc516] Delay the falling edge data from the IDDR primitive HOT 1
- [fmc516-sw] Support for multiple fmc516 cores (and boards...)
- [fmc516] Fix reserved register fields
- [fmc516] Implement synchronization between all data chains with a single clock domain HOT 2
- [fmc516] Implement automatic idelay selection
- [fmc516] fix multiple MMCM primitives in adc_clock.vhd HOT 1
- [dsp-devel][fmc516] ADC Data appears to be off by one cycle HOT 2
- [all] Unify SDB descriptors.
- [ddr3-core] Implement a DDR3 core wrapper for Xilinx MIG HOT 3
- Reimplement emb-sw fmc structures!
- [soon-to-be fmc-port] Add g_with_bufio and g_with_bufr HOT 1
- [fmc-adc-common] Fix BUFIO/BUFR/BUFG clk generation HOT 1
- [emb-sw] Consider moving the emb-sw folder to another git repository
- [fmc-adc-data] Check registers in the datapath to ease timing
- [ddr3-sdram] phy_init_done never asserted HOT 2
- [pcie-core] Fix missing signal HOT 1
- [wb_acq_core] Cleanup core and implement missing features
- [wb_acq_core] Add multiple "simultaneous" acquisition paths
- [wb_fmc130m_4ch] Add switching clock through MMCX connector
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