koheron / koheron-sdk Goto Github PK

SDK for FPGA / Linux Instruments

Home Page: https://www.koheron.com/software-development-kit/

License: Other

Makefile 2.26% Tcl 24.93% Verilog 5.04% Shell 1.14% Python 4.26% C++ 44.03% HTML 0.76% TypeScript 5.01% VHDL 7.30% C 4.79% CSS 0.23% Dockerfile 0.24%

fpga linux build zynq

koheron-sdk's Introduction

koheron-sdk

https://www.koheron.com/software-development-kit

Getting started

The SDK is tested on an Ubuntu 22.04 development machine.

Install Vivado. Instruments can be built on Vivado versions newer than 2017.2. The OS can only be built with Vivado 2017.2. The branch 2023.2 uses Vivado/Vitis 2023.2 and includes preliminary Zynq Utrascale support.
Install required packages
```
$ make setup
```
Install Ubuntu 22.04 for Zynq (Download SD card image)

Build and run an instrument

$ make CONFIG=examples/alpha250/adc-dac-bram/config.yml HOST=192.168.1.100 run
$ HOST=192.168.1.100 python3 examples/alpha250/adc-dac-bram/test.py

Ready to develop your instrument? Read the documentation.

Koheron Alpha250 designs

fft : reference design with spectrum analyzer, DDS and demodulation.
phase-noise-analyzer : phase noise analyzer.
loopback : minimal instrument.
adc-dac-bram : set DAC waveforms and get ADC using Block RAMs.
adc-dac-dma : set DAC waveforms and get ADC using DMA.

Red Pitaya designs

adc-dac : instrument with minimal read/write capability on Red Pitaya ADCs and DACs.
decimator : decimation using a compensated CIC filter.

How to

Build an instrument:

$ make CONFIG=path/to/config.yml

Build an instrument block design:

$ make CONFIG=path/to/config.yml block_design

More commands are listed in the documentation.

Acknowledgments

This project started as a fork of red-pitaya-notes.

koheron-sdk's People

Contributors

Stargazers

Watchers

Forkers

rollingstone archigithub grahamnaylorccfe xueshiguo muhammadmajidaltaf jinsanko shahbaazlokh mdh0815 diodo70 rudyma surgavery christeefym liuming15 voldmr rsarwar87 ninianhong gtrensch donrv smartiotmaker krih-krih labolas89 gflerm yen4322 llombard tucanae47 nickoko uniontm jeyhd weis888 bamiesking argillander vercingetorix-forks adamvstephen kordts ayaz345 designerguy13-photonics donzelot vitorbnc frontcover yeojunpark

koheron-sdk's Issues

/dev/mem docker

http://blog.hypriot.com/post/lets-get-physical/

Nous ne parvenons pas à exécuter les commandes make HOST= ... NAME=instrument run car il semble qu'il y ait un problème lors du chargement du bitstream via le serveur sur la carte Red Pitaya. Nous supposons que le proxy local empêche le transfert du bitstream. A noter que la machine de développement et la carte Red Pitaya sont sur le réseau général qui a accès à internet uniquement via un Proxy.

Configuration utilisée :

Nous avons suivi la documentation pour l'installation de la machine virtuelle :

image utilisée : led_blinker-37f1e22.img
gravée avec : Win32DiskImager-0.9.5-binary

Ces commandes s'exécutent de manière automatique sur la VM pour passer par le proxy de l'office lors du chargement d'une page web :

export http_proxy=http://proxy.office:80
<http://proxy.office:80>
export https_proxy=http://proxy.office:80
<http://proxy.office:80>
export ftp_proxy=http://proxy.office:80
<http://proxy.office:80>
export no_proxy="localhost,127.0.0.1"

Après avoir vérifié que l'IP de notre Red Pitaya sur le réseau général fonctionnait (avec ping 125.40.20.79), on vérifie que la connection ssh fonctionne :

devrp@devrp-VirtualBox:~/koheron-sdk$ ssh [email protected]
root@koheron:~#

Sur un autre terminal

devrp@devrp-VirtualBox: ~$ cd koheron-sdk/
devrp@devrp-VirtualBox:~/koheron-sdk$. settings.sh 
devrp@devrp-VirtualBox:~/koheron-sdk$ make HOST=125.40.20.79 NAME=adc_dac run
python scripts/make.py --live_zip adc_dac instruments
http://zynq-sdk.s3-website-eu-west-1.amazonaws.com/live-default.zip
[tmp/adc_dac.live] OK
zip --junk-paths tmp/adc_dac-8f7d9c4.zip tmp/adc_dac.bit tmp/adc_dac.live tmp/adc_dac.server.build/kserverd tmp/adc_dac.start.sh tmp/adc_dac.live/*
  adding: adc_dac.bit (deflated 92%)
  adding: kserverd (deflated 61%)
  adding: adc_dac.start.sh (deflated 49%)
  adding: default.js (deflated 69%)
  adding: index.html (deflated 70%)
[tmp/adc_dac-8f7d9c4.zip] OK
curl -v -F adc_dac-8f7d9c4.zip=@tmp/adc_dac-8f7d9c4.zip http://125.40.20.79/api/instruments/upload
*   Trying 125.40.20.79...
* Connected to 125.40.20.79 (125.40.20.79) port 80 (#0)
> POST /api/instruments/upload HTTP/1.1
> Host: 125.40.20.79
> User-Agent: curl/7.47.0
> Accept: */*
> Content-Length: 128353
> Expect: 100-continue
> Content-Type: multipart/form-data; boundary=------------------------da1b3088bb153802
> 
< HTTP/1.1 100 Continue
< HTTP/1.1 504 Gateway Time-out
< Server: nginx/1.10.0 (Ubuntu)
< Date: Thu, 11 Feb 2016 16:35:38 GMT
< Content-Type: text/html
< Content-Length: 192
< Connection: keep-alive
* HTTP error before end of send, stop sending
< 
<html>
<head><title>504 Gateway Time-out</title></head>
<body bgcolor="white">
<center><h1>504 Gateway Time-out</h1></center>
<hr><center>nginx/1.10.0 (Ubuntu)</center>
</body>
</html>
* Closing connection 0
curl http://125.40.20.79/api/instruments/run/adc_dac/8f7d9c4
<html>
<head><title>502 Bad Gateway</title></head>
<body bgcolor="white">
<center><h1>502 Bad Gateway</h1></center>
<hr><center>nginx/1.10.0 (Ubuntu)</center>
</body>
</html>

Il semblerait donc que la modification des fichiers de config du serveur #307 n'ait par résolu le problème auquel nous somme confronté, il nous est toujours pas possible d'utiliser les commandes make ..., au moment d'envoyer le bitstream sur la carte, un blocage s'effectue.

Comment pourrions nous faire en sorte de contourner ce problème ?

Merci d'avance
Yoann

Pulse generator instrument control using test.py

In the provided test.py program for the pulse generator instrument, I get the following error:

~/koheron-sdk$ python instruments/pulse_generator/test.py
Traceback (most recent call last):
File "instruments/pulse_generator/test.py", line 32, in
driver.set_dac()
File "/home/graham/koheron-sdk/instruments/pulse_generator/pulse.py", line 38, in set_dac
set_dac_data(self, dac_data_1 + 65536 * dac_data_2)
File "/home/graham/anaconda3/lib/python3.6/site-packages/koheron/koheron.py", line 98, in wrapper
self.client.send_command(device_id, cmd_id, cmd_args, *args)
File "/home/graham/anaconda3/lib/python3.6/site-packages/koheron/koheron.py", line 367, in send_command
cmd = make_command(device_id, cmd_id, cmd_args, *args)
File "/home/graham/anaconda3/lib/python3.6/site-packages/koheron/koheron.py", line 116, in make_command
buff += build_payload(args[2], args[3:])
File "/home/graham/anaconda3/lib/python3.6/site-packages/koheron/koheron.py", line 185, in build_payload
append_array(payload, args[i], get_std_array_params(arg['type']))
File "/home/graham/anaconda3/lib/python3.6/site-packages/koheron/koheron.py", line 147, in append_array
buff += bytearray(array)
TypeError: only integer arrays with one element can be converted to an index

I am running Python 3.6.0 :: Anaconda 4.3.0 (64-bit) (Ubuntu 16.04 VM).
Graham

Experiment with DMA

Interesting discussion from the Red Pitaya forum:
http://forum.redpitaya.com/viewtopic.php?f=14&t=551

Vivado Licence not found

When I try to build the bitstream with Vivado 2015.4, it fails with:

mkdir -p tmp
vivado -nolog -nojournal -mode batch -source scripts/hwdef.tcl -tclargs oscillo

****** Vivado v2015.4 (64-bit)
  **** SW Build 1412921 on Wed Nov 18 09:44:32 MST 2015
  **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source scripts/hwdef.tcl
# set project_name [lindex $argv 0]
# open_project tmp/$project_name.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/vanderbruggen/ownCloud/zynq-sdk/tmp/cores'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2015.4/data/ip'.
# if {[get_property PROGRESS [get_runs synth_1]] != "100%"} {
#   launch_runs synth_1
#   wait_on_run synth_1
# }
[Fri Dec 25 13:51:25 2015] Launched synth_1...
Run output will be captured here: /home/vanderbruggen/ownCloud/zynq-sdk/tmp/oscillo.runs/synth_1/runme.log
[Fri Dec 25 13:51:25 2015] Waiting for synth_1 to finish...

*** Running vivado
    with args -log system_wrapper.vds -m64 -mode batch -messageDb vivado.pb -notrace -source system_wrapper.tcl


****** Vivado v2015.4 (64-bit)
  **** SW Build 1412921 on Wed Nov 18 09:44:32 MST 2015
  **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source system_wrapper.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/vanderbruggen/ownCloud/zynq-sdk/tmp/cores'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2015.4/data/ip'.
Command: synth_design -top system_wrapper -part xc7z010clg400-1 -fanout_limit 400 -fsm_extraction one_hot -keep_equivalent_registers -resource_sharing off -no_lc -shreg_min_size 5
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010'
WARNING: [Common 17-348] Failed to get the license for feature 'Synthesis' and/or device 'xc7z010'
3 Infos, 1 Warnings, 0 Critical Warnings and 1 Errors encountered.
synth_design failed
ERROR: [Common 17-345] A valid license was not found for feature 'Synthesis' and/or device 'xc7z010'. Please run the Vivado License Manager for assistance in determining
which features and devices are licensed for your system.
Resolution: Check the status of your licenses in the Vivado License Manager. For debug help search Xilinx Support for "Licensing FAQ". 
INFO: [Common 17-206] Exiting Vivado at Fri Dec 25 13:51:35 2015...
[Fri Dec 25 13:51:39 2015] synth_1 finished
wait_on_run: Time (s): cpu = 00:00:02 ; elapsed = 00:00:14 . Memory (MB): peak = 1018.730 ; gain = 0.000 ; free physical = 657 ; free virtual = 10353
# write_hwdef -force -file tmp/$project_name.hwdef
# close_project
INFO: [Common 17-206] Exiting Vivado at Fri Dec 25 13:51:41 2015...
mkdir -p tmp/oscillo.fsbl
hsi -nolog -nojournal -mode batch -source scripts/fsbl.tcl -tclargs oscillo ps7_cortexa9_0

****** hsi v2015.4 (64-bit)
  **** SW Build 1412921 on Wed Nov 18 09:44:32 MST 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source scripts/fsbl.tcl
# set project_name [lindex $argv 0]
# set proc_name [lindex $argv 1]
# set hard_path tmp/$project_name.hard
# set fsbl_path tmp/$project_name.fsbl
# file mkdir $hard_path
# file copy -force tmp/$project_name.hwdef $hard_path/$project_name.hdf
# open_hw_design $hard_path/$project_name.hdf
# create_sw_design -proc $proc_name -os standalone fsbl
INFO: [Hsi 55-1698] elapsed time for repository loading 0 seconds
# add_library xilffs
# add_library xilrsa
# generate_app -proc $proc_name -app zynq_fsbl -dir $fsbl_path -compile
Running Make include in ps7_cortexa9_0/libsrc/bram_v4_0/src
Running Make include in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_2/src
Running Make include in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_1/src
Running Make include in ps7_cortexa9_0/libsrc/ddrps_v1_0/src
Running Make include in ps7_cortexa9_0/libsrc/devcfg_v3_3/src
Running Make include in ps7_cortexa9_0/libsrc/dmaps_v2_1/src
Running Make include in ps7_cortexa9_0/libsrc/emacps_v3_1/src
Running Make include in ps7_cortexa9_0/libsrc/gpiops_v3_1/src
Running Make include in ps7_cortexa9_0/libsrc/gpio_v4_0/src
Running Make include in ps7_cortexa9_0/libsrc/iicps_v3_0/src
Running Make include in ps7_cortexa9_0/libsrc/qspips_v3_2/src
Running Make include in ps7_cortexa9_0/libsrc/scugic_v3_1/src
Running Make include in ps7_cortexa9_0/libsrc/scutimer_v2_1/src
Running Make include in ps7_cortexa9_0/libsrc/scuwdt_v2_1/src
Running Make include in ps7_cortexa9_0/libsrc/sdps_v2_6/src
Running Make include in ps7_cortexa9_0/libsrc/spips_v3_0/src
Running Make include in ps7_cortexa9_0/libsrc/standalone_v5_3/src
Running Make include in ps7_cortexa9_0/libsrc/sysmon_v7_1/src
Running Make include in ps7_cortexa9_0/libsrc/ttcps_v3_0/src
Running Make include in ps7_cortexa9_0/libsrc/uartps_v3_1/src
Running Make include in ps7_cortexa9_0/libsrc/usbps_v2_2/src
Running Make include in ps7_cortexa9_0/libsrc/xadcps_v2_2/src
Running Make include in ps7_cortexa9_0/libsrc/xilffs_v3_1/src
Running Make include in ps7_cortexa9_0/libsrc/xilrsa_v1_1/src
Running Make libs in ps7_cortexa9_0/libsrc/bram_v4_0/src
Compiling bram
arm-xilinx-eabi-ar: creating ../../../lib/libxil.a
Running Make libs in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_2/src
Compiling coresightps_dcc
Running Make libs in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_1/src
Compiling cpu_cortexa9
Running Make libs in ps7_cortexa9_0/libsrc/ddrps_v1_0/src
Compiling ddrps
Running Make libs in ps7_cortexa9_0/libsrc/devcfg_v3_3/src
Compiling devcfg
Running Make libs in ps7_cortexa9_0/libsrc/dmaps_v2_1/src
Compiling dmaps
Running Make libs in ps7_cortexa9_0/libsrc/emacps_v3_1/src
Compiling emacps
Running Make libs in ps7_cortexa9_0/libsrc/gpiops_v3_1/src
Compiling gpiops
Running Make libs in ps7_cortexa9_0/libsrc/gpio_v4_0/src
Compiling gpio
Running Make libs in ps7_cortexa9_0/libsrc/iicps_v3_0/src
Compiling iicps
Running Make libs in ps7_cortexa9_0/libsrc/qspips_v3_2/src
Compiling qspips
Running Make libs in ps7_cortexa9_0/libsrc/scugic_v3_1/src
Compiling scugic
Running Make libs in ps7_cortexa9_0/libsrc/scutimer_v2_1/src
Compiling scutimer
Running Make libs in ps7_cortexa9_0/libsrc/scuwdt_v2_1/src
Compiling scuwdt
Running Make libs in ps7_cortexa9_0/libsrc/sdps_v2_6/src
Compiling sdps
Running Make libs in ps7_cortexa9_0/libsrc/spips_v3_0/src
Compiling spips
Running Make libs in ps7_cortexa9_0/libsrc/standalone_v5_3/src
Compiling standalone
Running Make libs in ps7_cortexa9_0/libsrc/sysmon_v7_1/src
Compiling sysmon
Running Make libs in ps7_cortexa9_0/libsrc/ttcps_v3_0/src
Compiling ttcps
Running Make libs in ps7_cortexa9_0/libsrc/uartps_v3_1/src
Compiling uartps
Running Make libs in ps7_cortexa9_0/libsrc/usbps_v2_2/src
Compiling usbps
Running Make libs in ps7_cortexa9_0/libsrc/xadcps_v2_2/src
Compiling xadcps
Running Make libs in ps7_cortexa9_0/libsrc/xilffs_v3_1/src
Compiling XilFFs Library
Running Make libs in ps7_cortexa9_0/libsrc/xilrsa_v1_1/src
Finished building libraries
generate_target: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 406.582 ; gain = 0.000 ; free physical = 796 ; free virtual = 10506
gmake[1]: Entering directory `/home/vanderbruggen/ownCloud/zynq-sdk/tmp/oscillo.fsbl'
arm-xilinx-eabi-gcc  -MMD -MP -c fsbl_hooks.c -o fsbl_hooks.o -Izynq_fsbl_bsp/ps7_cortexa9_0/include -I.
arm-xilinx-eabi-gcc  -MMD -MP -c image_mover.c -o image_mover.o -Izynq_fsbl_bsp/ps7_cortexa9_0/include -I.
arm-xilinx-eabi-gcc  -MMD -MP -c main.c -o main.o -Izynq_fsbl_bsp/ps7_cortexa9_0/include -I.
arm-xilinx-eabi-gcc  -MMD -MP -c md5.c -o md5.o -Izynq_fsbl_bsp/ps7_cortexa9_0/include -I.
arm-xilinx-eabi-gcc  -MMD -MP -c nand.c -o nand.o -Izynq_fsbl_bsp/ps7_cortexa9_0/include -I.
arm-xilinx-eabi-gcc  -MMD -MP -c nor.c -o nor.o -Izynq_fsbl_bsp/ps7_cortexa9_0/include -I.
arm-xilinx-eabi-gcc  -MMD -MP -c pcap.c -o pcap.o -Izynq_fsbl_bsp/ps7_cortexa9_0/include -I.
arm-xilinx-eabi-gcc  -MMD -MP -c ps7_init.c -o ps7_init.o -Izynq_fsbl_bsp/ps7_cortexa9_0/include -I.
arm-xilinx-eabi-gcc  -MMD -MP -c qspi.c -o qspi.o -Izynq_fsbl_bsp/ps7_cortexa9_0/include -I.
arm-xilinx-eabi-gcc  -MMD -MP -c rsa.c -o rsa.o -Izynq_fsbl_bsp/ps7_cortexa9_0/include -I.
arm-xilinx-eabi-gcc  -MMD -MP -c sd.c -o sd.o -Izynq_fsbl_bsp/ps7_cortexa9_0/include -I.
arm-xilinx-eabi-gcc  -MMD -MP -c fsbl_handoff.S -o fsbl_handoff.o -Izynq_fsbl_bsp/ps7_cortexa9_0/include -I.
arm-xilinx-eabi-gcc -o executable.elf  fsbl_hooks.o  image_mover.o  main.o  md5.o  nand.o  nor.o  pcap.o  ps7_init.o  qspi.o  rsa.o  sd.o  fsbl_handoff.o   -MMD -MP -lrsa -Wl,--start-group,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxilffs,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lrsa,-lxil,-lgcc,-lc,--end-group  -Wl,--gc-sections -Lzynq_fsbl_bsp/ps7_cortexa9_0/lib -L./ -Tlscript.ld
gmake[1]: Leaving directory `/home/vanderbruggen/ownCloud/zynq-sdk/tmp/oscillo.fsbl'
generate_app: Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 406.582 ; gain = 0.000 ; free physical = 799 ; free virtual = 10505
# close_hw_design [current_hw_design]
INFO: [Common 17-206] Exiting hsi at Fri Dec 25 13:51:59 2015...
mkdir -p tmp
vivado -nolog -nojournal -mode batch -source scripts/bitstream.tcl -tclargs oscillo

****** Vivado v2015.4 (64-bit)
  **** SW Build 1412921 on Wed Nov 18 09:44:32 MST 2015
  **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source scripts/bitstream.tcl
# set project_name [lindex $argv 0]
# open_project tmp/$project_name.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/vanderbruggen/ownCloud/zynq-sdk/tmp/cores'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2015.4/data/ip'.
# if {[get_property PROGRESS [get_runs impl_1]] != "100%"} {
#   launch_runs impl_1 -to_step route_design
#   wait_on_run impl_1
# }
ERROR: [Common 17-70] Application Exception: Failed to launch run 'impl_1' due to failures in the following run(s):
synth_1
These failed run(s) need to be reset prior to launching 'impl_1' again.

INFO: [Common 17-206] Exiting Vivado at Fri Dec 25 13:52:09 2015...
make: *** [tmp/oscillo.bit] Error 1

Also I have to run the make in superuser.

Core build fails

I forgot to run source settings.sh and ran the build. The build failed so I ran source settings.sh and ran the build again. The build failed again.

I had to do a make clean and restart the build.

so what's next?

Once the 3 commands are performed
$ make NAME=<project> zip
$ make NAME=<project>
$ sudo bash scripts/image.sh <project>
well... what's next?

/tmp/instrument/spectrum.start.sh: No such file or directory

With the last version of the app:

[notice] Start last deployed instrument
Installing instrument spectrum with version 0c06b28
Archive:  /usr/local/instruments/spectrum-0c06b28.zip
inflating: /tmp/instrument/spectrum.bit
 inflating: /tmp/instrument/kserverd
api_app/install_instrument.sh: line 12: /tmp/instrument/spectrum.start.sh: No such file or directory
 Failed to connect to 127.0.0.1:36000 : [Errno 111] Connection refused

Building new fpga cores for the SDK

According to the documentation, a new fpga core can be built and tested using a command such as:
$ make CORE=my_core test_core
What are the pre-requisites to be able to run this command? Does it expect a verilog file called my_core in a subdirectory to fpga/cores/test_core along with a core_config.tcl file? When I try this mix I either get an error - "*** No rule to make target...", or if I am in the directory fpga/cores I get the error "Nothing to be done" (and no cores built in the tmp/cores directory). Is something else expected before it will build the core?
thanks
Graham

DTC not found

During u-boot compilation, it fails with:

/bin/sh: 1: dtc: not found
make[3]: *** [arch/arm/dts/zynq-zc702.dtb] Error 127
make[2]: *** [arch-dtbs] Error 2
make[1]: *** [dts] Error 2
make[1]: Leaving directory `/home/vanderbruggen/ownCloud/zynq-sdk/tmp/u-boot-xlnx-xilinx-v2015.4'
make: *** [tmp/u-boot.elf] Error 2

Makefile tricks

http://stackoverflow.com/questions/6767413/create-a-variable-in-a-makefile-by-reading-contents-of-another-file

start.sh

At instrument starting:

Installing instrument oscillo with version e196fcb
Archive:  /usr/local/instruments/oscillo-e196fcb.zip
 inflating: /tmp/instrument/oscillo.bit
 inflating: /tmp/instrument/kserverd
  inflating: /tmp/instrument/oscillo.start.sh
Clock initialization...
line 7: local: `=': not a valid identifier
line 8: local: `=': not a valid identifier
/tmp/instrument/oscillo.start.sh: line 8: local: `200000000': not a valid identifier
/tmp/instrument/oscillo.start.sh: line 9: echo: write error: Invalid argument
/tmp/instrument/oscillo.start.sh: line 10: /sys/devices/soc0/amba/f8007000.devcfg/fclk//enable: No such file or directory
/tmp/instrument/oscillo.start.sh: line 11: /sys/devices/soc0/amba/f8007000.devcfg/fclk//set_rate: No such file or directory
/tmp/instrument/oscillo.start.sh: line 7: local: `=': not a valid identifier
/tmp/instrument/oscillo.start.sh: line 8: local: `=': not a valid identifier
/tmp/instrument/oscillo.start.sh: line 8: local: `200000000': not a valid identifier
/tmp/instrument/oscillo.start.sh: line 9: echo: write error: Invalid argument
/tmp/instrument/oscillo.start.sh: line 10: /sys/devices/soc0/amba/f8007000.devcfg/fclk//enable: No such file or directory
/tmp/instrument/oscillo.start.sh: line 11: /sys/devices/soc0/amba/f8007000.devcfg/fclk//set_rate: No such file or directory
Load bitstream
1
Restart tcp-server

Running perf on Zynq

To build perf for the zynq you need:

sudo apt-get install flex bison

Then build:

make -C tmp/linux-xlnx-xilinx-v2015.4/tools/perf ARCH=arm CFLAGS="-O2 -mtune=cortex-a9 -mfpu=neon -mfloat-abi=softfp" CROSS_COMPILE=/usr/bin/arm-linux-gnueabihf-

By doing so I ran into the error:

builtin-report.c: In function ‘cmd_report’:
builtin-report.c:769:23: error: comparison of constant ‘-1’ with boolean expression is always false [-Werror=bool-compare]
      branch_call_mode == -1) {

Removing out the faulty line (not sure what I messed up with):

if (((branch_mode == -1 && has_br_stack) || branch_mode == 1))  {
    sort__mode = SORT_MODE__BRANCH;
    symbol_conf.cumulate_callchain = false;
}

instead of

if (((branch_mode == -1 && has_br_stack) || branch_mode == 1) &&
       branch_call_mode == -1) {
    sort__mode = SORT_MODE__BRANCH;
    symbol_conf.cumulate_callchain = false;
}

it compiles and the executable runs on the Zynq. At least for simple

perf record [prog]
perf report

Requirements on Ubuntu 16.04

Install Xilinx Vivado 2016.1 #101

sudo apt-get install git python-virtualenv g++-arm-linux-gnueabihf lib32stdc++6 lib32z1\
                     u-boot-tools libssl-dev device-tree-compiler qemu-user-static curl

sudo ln -s make /usr/bin/gmake
sudo easy_install pip

Finding the IP address of the Koheron instrument

Comment not an issue:
I have not been able to use the methods given on the support pages to find the IP address of a Koheron instrument plugged in to a local router (simply didn't show up on the Windows control pan in Network and sharing centre), however what does seem to work in Linux and Windows is to simply type in to a terminal window:
nslookup koheron

If there are going to be many instruments on the network, then it might be worth editing the hostnames in /etc/hostnames and /etc/hosts so as to be able to distinguish them.
Graham

Vivado ERROR: [DRC 23-20] Rule violation

Bonjour l'équipe,

J'utilise actuellement la version d'OS 806de7a.
Je cherche à renvoyer des signaux internes vers différentes IO (Extension connectors de la Red Pitaya). J'avais déjà effectué la manip il y a quelques temps et cela fonctionnait très bien.
Je rencontre donc un problème que je n'avais pas avant, sans parvenir à comprendre à quoi cela peut-être dû.

ERROR: [DRC 23-20] Rule violation (BIVC-1) Bank IO standard Vcc - Conflicting Vcc voltages in bank 35. For example, the following two ports in this bank have conflicting VCCOs: valid_DAC (LVCMOS18, requiring VCCO=1.800) and valid_ADC (LVCMOS33, requiring VCCO=3.300)

J'utilise un fichier de contrainte supplémentaire (en plus de ports.xdc et de clocks.xdc) que j'ai créé dans le dossier de mon instrument (ports_trig.xdc) et qui comprend ces quatres lignes :

set_property IOSTANDARD LVCMOS33 [get_ports valid_ADC]
set_property IOSTANDARD LVCMOS33 [get_ports valid_ADC]
set_property PACKAGE_PIN H16 [get_ports valid_DAC]
set_property PACKAGE_PIN H17 [get_ports valid_ADC]

J'ai déclaré ce fichier de contrainte dans mon fichier de config.yml de l'instrument :

xdc:
  - boards/red-pitaya/config/ports.xdc
  - boards/red-pitaya/config/clocks.xdc
  - instruments/pulse_generator_moyennage/ports_trig.xdc

Je souhaite donc sortir deux signaux différents sur les pins H16 et H17 qui sont alimentées en 3.3V conformément à la documentation.

Je connecte mes "fils" à ces ports de sortie de cette manière :

create_bd_port -dir O valid_DAC
create_bd_port -dir O valid_ADC

connect_bd_net [get_bd_ports valid_DAC] [get_bd_pins averager_delayed/valid]
connect_bd_net [get_bd_ports valid_ADC] [get_bd_pins averager_delayed/first_acq_data]

Je pense avoir donc procédé de la bonne manière pour sortir mes signaux mais il semble que l'étape DRC persiste à trouver un conflit dans les tensions d'alimentations de ces pins qui ne sont attribuées que dans mon fichier ports_trig.xdc . Il semble que je ne sois pas le seul à avoir rencontré ce problème (lien forum) et qu'il puisse se résoudre en supprimant et rechargeant les fichiers de contraintes et fichiers sources. Malheureusement, en utilisant votre méthode de prototypage, je ne créé pas de projet Vivado au sens propre dans lequel j'ajouterai des fichiers au fur et à mesure et je ne vois donc pas comment je peux procéder pour résoudre cette erreur (?). J'ai tenté de faire un clean_instrument mais cela n'a rien apporté.

Auriez vous des suggestions pour résoudre mon soucis ?

Merci d'avance

Yoann

Network tricks

Scan IP addresses

sudo nmap -sP 192.168.1.0/24

long compilation time

Short question: since 0.13, compilation time is much longer. Maybe because:

`Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Place 46-20] Placer is running with the ExtraNetDelay_high directive. Post Placement Optimization may take longer to complete with ExtraNetDelay_high compared to other directives.
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=0.170. For the most accurate timing information please run report_timing.
Phase 4.1.1 Post Placement Optimization | Checksum: 2246f81ac

Time (s): cpu = 00:14:08 ; elapsed = 00:14:12 . Memory (MB): peak = 1982.391 ; gain = 3.012 ; free physical = 3477 ; free virtual = 8666
Phase 4.1 Post Commit Optimization | Checksum: 2246f81ac

Time (s): cpu = 00:14:08 ; elapsed = 00:14:12 . Memory (MB): peak = 1982.391 ; gain = 3.012 ; free physical = 3477 ; free virtual = 8666

Phase 4.2 Post Placement Cleanup
`
Is this directive useful?
(14 minutes for this 4.1.1 step)

v0.13 : ERROR: [DRC 23-20] Rule violation (LUTLP-1) Combinatorial Loop Alert

Dear Koheron

Have you seen this kind of error? It prevents successful compilation:

`Generating merged BMM file for the design top 'system_wrapper'...
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 610 instances were transformed.
  RAM16X1D => RAM32X1D (RAMD32, RAMD32): 4 instances
  RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 30 instances
  RAM64M => RAM64M (RAMD64E, RAMD64E, RAMD64E, RAMD64E): 448 instances
  RAM64X1D => RAM64X1D (RAMD64E, RAMD64E): 128 instances

open_run: Time (s): cpu = 00:00:22 ; elapsed = 00:00:22 . Memory (MB): peak = 1793.309 ; gain = 765.941 ; free physical = 315 ; free virtual = 8430
# set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
# set_property BITSTREAM.GENERAL.XADCENHANCEDLINEARITY On [current_design]
# write_bitstream -force -file tmp/$instrument_name.bit
Command: write_bitstream -force -file tmp/tof_redpitaya_boite_ll2.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
Running DRC as a precondition to command write_bitstream
INFO: [DRC 23-27] Running DRC with 4 threads
ERROR: [DRC 23-20] Rule violation (LUTLP-1) Combinatorial Loop Alert - 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any net in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [net_nets <myHier/myNet>'. The cells in the loop are: system_i/module_boite_ll2/compteur_moyenne_tvalid_tof/inst/ena_bram_i_1.
WARNING: [DRC 23-20] Rule violation (CHECK-3) Report rule limit reached - REQP-1839 rule limit reached: 20 violations have been found.
`
(... 20 warnings)

`INFO: [Vivado 12-3199] DRC finished with 1 Errors, 21 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run.
INFO: [Common 17-83] Releasing license: Implementation
5 Infos, 21 Warnings, 0 Critical Warnings and 2 Errors encountered.
write_bitstream failed
ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors.

    while executing
"write_bitstream -force -file tmp/$instrument_name.bit"
    (file "fpga/scripts/bitstream.tcl" line 16)
INFO: [Common 17-206] Exiting Vivado at Mon Feb 20 13:27:38 2017...
Makefile:213: recipe for target 'tmp/tof_redpitaya_boite_ll2.bit' failed
make: *** [tmp/tof_redpitaya_boite_ll2.bit] Error 1

This occurs since version 0.13 (used to compile with 0.10).

be careful to use git clone command...

... otherwise you get
make: *** No rule to make target.git/refs/heads', needed by tmp/blink.version'. Stop. Command-line invocation: "make NAME=blink zip"
when trying to make the project (.git folder is not included in zip file repository)

Errors while executing ./fpga/vivado/project.tcl

Just trying to get my head around all the changes in the latest version. I hope that you expect to maintain the current conventions going forwards?
The changes seem quite profound and porting an old design seems to be taking quite a while (not got to the web part yet...)!

Clock Domain Crossing

https://filebox.ece.vt.edu/~athanas/4514/ledadoc/html/pol_cdc.html

rp_remote_acquire equivalent?

Dear Koheron team,

this is more a request than an issue.

I would like to get ADC time series as fast as possible by UDP (the protocol used by rp_remote_acquire that is not compatible with current versions of ecosystem) or, if not possible, by TCP.
UDP and TCP allows to receive data in Labview for example ;-)

example speed test with rp_remote_acquire:
Koheron/laser-development-kit#50

Any solution ?
Thanks :)
Laurent

ImportError: /opt/Xilinx/Vivado/2016.2/lib/lnx64.o/libstdc++.so.6: version `GLIBCXX_3.4.21' not found

This problem happens when running some programs under Ubuntu 16.04 when Vivado 2016.2 settings are sourced. The following programs seems to be incompatible with Vivado:

gedit
scipy
matplotlib

The solution is to tell Vivado to use the system version of libstdc++.so.6 instead of the one used by Vivado:

sudo mv /opt/Xilinx/Vivado/2016.2/lib/lnx64.o/libstdc++.so.6 /opt/Xilinx/SDK/2016.2/lib/lnx64.o/libstdc++.so.6.orig
sudo ln -s /usr/lib/x86_64-linux-gnu/libstdc++.so.6.0.21 /opt/Xilinx/Vivado/2016.2/lib/lnx64.o/libstdc++.so.6

Idem for Xilinx SDK:

sudo mv /opt/Xilinx/SDK/2016.2/lib/lnx64.o/libstdc++.so.6 /opt/Xilinx/SDK/2016.2/lib/lnx64.o/libstdc++.so.6.orig
sudo ln -s /usr/lib/x86_64-linux-gnu/libstdc++.so.6.0.21 /opt/Xilinx/SDK/2016.2/lib/lnx64.o/libstdc++.so.6

Building project to an SD card image

Previously the method of building an SD card image from scratch was to first build the PL design in Vivado and then create the OS from the latest Ubuntu using the command:

make CONFIG=instruments/my_instrument linux
Has this command now been deprecated in the latest version?

Make workflow compatible with Windows

It should be possible to:

Build the FPGA bitstream from Windows.
Control the FPGA from Windows-compatible Python scripts

The Linux distribution is painful to build on Windows.
Windows users can just upload and burn the standard SD-card image.

Interesting Zynq boards

Requirements on Ubuntu 14.04

Requirements

Install Xilinx Vivado 2015.4 #37

sudo apt-get install git python-virtualenv g++-arm-linux-gnueabihf lib32stdc++6 lib32z1 \
                     u-boot-tools libssl-dev device-tree-compiler qemu-user-static curl
sudo ln -s make /usr/bin/gmake
sudo pip install -r requirements.txt

Upgrade the ARM toolchain to GCC 5:

sudo apt-add-repository "deb http://fr.archive.ubuntu.com/ubuntu/ wily main"
sudo apt-get update
sudo apt-get install g++-5-arm-linux-gnueabihf
sudo rm -f /usr/bin/arm-linux-gnueabihf-gcc /usr/bin/arm-linux-gnueabihf-g++
sudo ln -s /usr/bin/arm-linux-gnueabihf-gcc-5 /usr/bin/arm-linux-gnueabihf-gcc
sudo ln -s /usr/bin/arm-linux-gnueabihf-g++-5 /usr/bin/arm-linux-gnueabihf-g++
sudo apt-add-repository  --remove "deb http://fr.archive.ubuntu.com/ubuntu/ wily main"

Install Vivado HLx 2015.4 on Ubuntu 14.04

The High Level Synthesis Tool is now available in all versions of vivado (including the free WebPACK version). To reflect this change, Vivado has been renamed to Vivado HLx. Here is how to install the free version of Vivado HLx on Ubuntu:

Go to the Xilinx Download Page:
http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/2015-4.html
Select Vivado HLx 2015.4 WebInstall for Linux with SDK
Enter your Xilinx credentials and download the executable
Run the executable:

cd ~/Downloads/
chmod +x Xilinx_Vivado_SDK_2015.4_1118_2_Lin64.bin
sudo ./Xilinx_Vivado_SDK_2015.4_1118_2_Lin64.bin

Follow the instructions

⚠️ don't forget to select Software Development Kit

Autocompletion

# apt-get install bash-completion

Edit /root/.bashrc

command "make NAME=averager INSTRUMENT_PATH=fpga/modules test_module failed

Bonjour,

J'ai voulu tester le module de moyenne pour comprendre un peu mieux son fonctionnement mais la commande ne semble pas aboutir. J'ai copié la commande que tu indiques sur le quick start pour tester le fonctionnement d'un module :

devrp@devrp-VirtualBox:~/koheron-sdk$` make NAME=averager INSTRUMENT_PATH=fpga/modules test_module
Traceback (most recent call last):
  File "scripts/make.py", line 237, in <module>
    dump_if_has_changed(os.path.join('tmp', instrument + '.drivers.yml'), cfg['server'])
KeyError: 'server'
Traceback (most recent call last):
  File "scripts/make.py", line 272, in <module>
    drivers = yaml.load(drivers_file)['server']
KeyError: 'server'
make: ***  Aucune règle pour fabriquer la cible « tmp/averager.config.yml », nécessaire pour « tmp/averager.config.tcl ». Arrêt.

AXI GPIO

http://www.xilinx.com/support/documentation/ip_documentation/axi_gpio/v2_0/pg144-axi-gpio.pdf

Configuration en IP statique

en local (sans DHCP), toutes les leds s'allument jusqu'à la 7 inclue et impossible de pinger 192.168.1.255 (ou d'autres). Le PC est bien configuré en 192.168.1.101 et 255.255.255.0. En revanche le DHCP fonctionne.

The server encountered an internal error and was unable to complete your request.

Dear Koheron developers,

we get the following error:

devrp@devrp-VirtualBox:~/koheron-sdk$ make NAME=led_blinker HOST=125.40.0.159 run
test -d tmp/koheron_server_venv || (virtualenv tmp/koheron_server_venv && \
			tmp/koheron_server_venv/bin/pip install -r tmp/led_blinker.koheron-server/requirements.txt)
python scripts/make.py --live_zip instruments/led_blinker 0.13.1 https://s3.eu-central-1.amazonaws.com/koheron-sdk
[tmp/led_blinker.live] OK
curl -v -F led_blinker-d2deb66.zip=@tmp/led_blinker-d2deb66.zip http://125.40.0.159/api/instruments/upload
*   Trying 125.40.0.159...
* Connected to 125.40.0.159 (125.40.0.159) port 80 (#0)
> POST /api/instruments/upload HTTP/1.1
> Host: 125.40.0.159
> User-Agent: curl/7.47.0
> Accept: */*
> Content-Length: 103510
> Expect: 100-continue
> Content-Type: multipart/form-data; boundary=------------------------d4564d03d131d166
> 
< HTTP/1.1 100 Continue
< HTTP/1.1 200 OK
< Server: nginx/1.10.0 (Ubuntu)
< Date: Thu, 11 Feb 2016 16:28:46 GMT
< Content-Type: text/html; charset=utf-8
< Content-Length: 44
< Connection: keep-alive
< 
* Connection #0 to host 125.40.0.159 left intact
Instrument led_blinker-d2deb66.zip uploaded.curl http://125.40.0.159/api/instruments/run/led_blinker/d2deb66
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2 Final//EN">
<title>500 Internal Server Error</title>
<h1>Internal Server Error</h1>
<p>The server encountered an internal error and was unable to complete your request.  Either the server is overloaded or there is an error in the application.</p>

when trying to follow the procedure on:
https://github.com/Koheron/koheron-sdk
the only difference being Vivado is in 2016.2 instead of 2016.4.

Access XADC from the FPGA

XADC Guide

HTTP API

Instruments

GET api/instruments/update
GET api/instruments/run/{name}/{version}
GET api/instruments/delete/{name}/{version}
GET api/instruments/upload/{name}/{version}
POST api/instruments/upload
GET api/instruments/local
GET api/instruments/live
GET api/instruments/restore

Board

GET api/board/reboot
GET api/board/version
GET api/board/dna
GET api/board/bitstream_id
GET api/board/ping

HTTP API (itself)

POST api/app/update
GET api/app/version
GET api/app/remote

Static content

GET api/static/update
POST api/static/upload

Koheron upgrade

I have been trying to upgrade to version 0.14 so ran:
pip install --upgrade koheron
(I am using python 2.7). The upgrade seems to go OK, but when I type:
koheron version
I get:
ImportError: No module named python.cli
I can't find any info on what python.cli is.
Any ideas what the issue is?
thanks
Graham

Install Vivado 2015.3 on Ubuntu 14.04

Go to the Xilinx Download Page:
http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/2015-3.html
Select Vivado 2015.3 WebInstall for Linux with SDK
Enter your Xilinx credentials and download the executable
Run the executable:

cd ~/Downloads/
chmod +x Xilinx_Vivado_SDK_2015.3_0929_1_Lin64.bin
sudo ./Xilinx_Vivado_SDK_2015.3_0929_1_Lin64.bin

Follow the instructions

⚠️ don't forget to select Software Development Kit

New instrument not starting

So I am in business creating new instruments now and so have been able to create the necessary source components for the new instrument called neutron_detector and so ran:

make NAME=neutron_detector

This seemed to proceed correctly, terminating OK with:

................................
Writing bitstream tmp/neutron_detector.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Common 17-83] Releasing license: Implementation
write_bitstream: Time (s): cpu = 00:00:17 ; elapsed = 00:00:16 . Memory (MB): peak = 2149.918 ; gain = 388.734 ; free physical = 4215 ; free virtual = 18637
# close_project
INFO: [Common 17-206] Exiting Vivado at Fri Dec 16 15:33:32 2016...
[tmp/neutron_detector.bit] OK
python scripts/make.py --start_sh neutron_detector instruments
[tmp/neutron_detector.start.sh] OK
python scripts/make.py --live_zip neutron_detector instruments 0.12.0 https://s3.eu-central-1.amazonaws.com/koheron-sdk
[tmp/neutron_detector.live] OK
zip --junk-paths tmp/neutron_detector-58873a7.zip tmp/neutron_detector.bit tmp/neutron_detector.live tmp/neutron_detector.server.build/kserverd tmp/neutron_detector.start.sh tmp/neutron_detector.live/*
  adding: neutron_detector.bit (deflated 87%)
  adding: kserverd (deflated 61%)
  adding: neutron_detector.start.sh (deflated 49%)
  adding: default.js (deflated 72%)
  adding: index.html (deflated 63%)
[tmp/neutron_detector-58873a7.zip] OK

I then uploaded the zip file from the tmp directory using
koheron --host=10.210.1.142 upload neutron_detector-58873a7.zip (with the correct IP for my RP)
The new instrument then appears on the web page of the RP. I click Launch, but the device seems to hang and the View button does not seem to work. A previous simple project to give a count on the LEDs seemed to work. When launching, the new instrument .bit file seems to appear in the /tmp/instrument directory on the RP, however when I try to launch the neutron_detector app the bit file and ...start.sh file seem to still be those for the previously launched instrument. Any idea what is stopping the server and bit file being loaded correctly?
thanks
Graham

SIGBUS on FIFO reading

SIGBUS is sometimes raised when reading FIFO data:

Program received signal SIGBUS, Bus error.
[Switching to Thread 0xb41ff450 (LWP 5784)]
0x0006111a in Klib::ReadReg32 (addr=3042365472) at middleware/drivers/wr_register.hpp:49
49  middleware/drivers/wr_register.hpp: No such file or directory.
(gdb) backtrace
#0  0x0006111a in Klib::ReadReg32 (addr=3042365472) at middleware/drivers/wr_register.hpp:49
#1  0x00061e62 in FIFOReader<65536u>::acquisition_thread_call (this=0xb552c044, acq_period=1000) at middleware/drivers/lib/fifo_reader.hpp:110
#2  0x000638c0 in std::_Mem_fn<void (FIFOReader<65536u>::*)(unsigned int)>::operator()<unsigned int, void>(FIFOReader<65536u>*, unsigned int&&) const (this=0xb4a10c44, 
    __object=0xb552c044) at /opt/Xilinx/SDK/2015.4/gnu/aarch32/lin/gcc-arm-linux-gnueabi/arm-linux-gnueabihf/include/c++/4.8.3/functional:601
#3  0x00063838 in std::_Bind_simple<std::_Mem_fn<void (FIFOReader<65536u>::*)(unsigned int)> (FIFOReader<65536u>*, unsigned int)>::_M_invoke<0u, 1u>(std::_Index_tuple<0u, 1u>) (this=0xb4a10c3c) at /opt/Xilinx/SDK/2015.4/gnu/aarch32/lin/gcc-arm-linux-gnueabi/arm-linux-gnueabihf/include/c++/4.8.3/functional:1732
#4  0x00063714 in std::_Bind_simple<std::_Mem_fn<void (FIFOReader<65536u>::*)(unsigned int)> (FIFOReader<65536u>*, unsigned int)>::operator()() (this=0xb4a10c3c)
    at /opt/Xilinx/SDK/2015.4/gnu/aarch32/lin/gcc-arm-linux-gnueabi/arm-linux-gnueabihf/include/c++/4.8.3/functional:1720
#5  0x000636ce in std::thread::_Impl<std::_Bind_simple<std::_Mem_fn<void (FIFOReader<65536u>::*)(unsigned int)> (FIFOReader<65536u>*, unsigned int)> >::_M_run() (
    this=0xb4a10c30) at /opt/Xilinx/SDK/2015.4/gnu/aarch32/lin/gcc-arm-linux-gnueabi/arm-linux-gnueabihf/include/c++/4.8.3/thread:115
#6  0xb6fb6854 in ?? () from /usr/lib/arm-linux-gnueabihf/libstdc++.so.6
Backtrace stopped: previous frame identical to this frame (corrupt stack?)

Dmesg gives:

Unhandled fault: external abort on non-linefetch (0x1018) at 0xb556d020

Meaning that we are trying to read an address that is not mapped (http://stackoverflow.com/questions/15889483/what-do-these-kernel-panic-errors-mean)

How to parse a YAML configuration file in Tcl ?

http://wiki.tcl-lang.org/4284

minor cell improvement

Hello,

Your averaging.tcl and spectrum.tcl code looks impressive!

I propose to make this code slightly cleaner by removing all the list commands and all the backslashes.

If you replace foreach {prop_name prop_value} $cell_props with foreach {prop_name prop_value} [subst $cell_props] and foreach {local_name remote_name} $cell_ports with foreach {local_name remote_name} [subst $cell_ports] in scripts/project.tcl, then all the [list ...] blocks could be replaced with {...} without backslashes.

Best regards,

Pavel

Verilog ressources

http://web.engr.oregonstate.edu/~traylor/ece474/lecture_verilog/beamer/verilog_operators.pdf

Starting point

red-pitaya-notes seems to be a very nice starting point for this project.

difficulties with proxies

During make process, python tries to install automatically yaml from virtualenv, and do not use system wide proxy setting. The installer does not find the server and stops.
Any suggestion?

Add Test Benches

Ressources

How to script Test Benches ?

Install Vivado HLx 2016.1 on Ubuntu 16.04

Go to the Xilinx Download Page:
http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/2016-1.html
Select Vivado HLx 2016.1: WebPACK and Editions - Linux Self Extracting Web Installer
Enter your Xilinx credentials and download the executable
Run the executable:

cd ~/Downloads/
chmod +x Xilinx_Vivado_SDK_2016.1_0409_1_Lin64.bin
sudo ./Xilinx_Vivado_SDK_2016.1_0409_1_Lin64.bin

Follow the instructions

⚠️ don't forget to select Software Development Kit

TCL tricks

Problème utilisation librairie koheron avec "connect"

Bonjour l'équipe Koheron,

En ayant la dernière version d'OS proposée (806de7a) ainsi qu'avec le dernier environnement de Koheron-sdk, voilà le message d'erreur que j'obtiens après avoir généré le bitstream d'un instrument puis essayé d'utiliser de fichier de "test.py".

Commandes pour l'installation de l'environnement

$ git clone https://github.com/Koheron/koheron-sdk $ cd koheron-sdk $ sudo pip install -r requirements.txt

Message d'erreur retourné

devrp@devrp-VirtualBox:~/koheron-sdk/instruments/adc_dac$ python test.py Traceback (most recent call last): File "test.py", line 5, in <module> from koheron import command, connect ImportError: cannot import name connect

Auriez vous une idée de l'origine du problème ?

Merci d'avance,
Yoann

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