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16-bit-custom-microprocessor-design-on-zynq-7000

Processor was Harvard architecture based as well as had its own instruction set format which required 4-6 machine clock cycles to complete instruction execution. Instructions such as Load/Store, ALU, Conditional Branching and Jumping along with software interrupt were primarily set-up with the possibility to add new instructions.

amp-zynq

Simple AMP Running Linux and Bare-Metal System on Both Zynq SoC Processors

aobench-zynqfb

aobench on zynq framebuffer

arduino-vivado-sdk

Arduino library for Microblaze and Cortex A9, integrated with Vivado/SDK

arty-chronicles

MicroBlaze code based on the Digilent Arty Board

arty_microblaze

Test project running a MicroBlaze soft processor on an Artix-7 FPGA board

artyproject

Arty Project Arty is a ready-to-use development platform designed around the Artix-7™ Field Programmable Gate Array (FPGA) from Xilinx. It was designed specifically for use as a MicroBlaze Soft Processing System. When used in this context, Arty becomes the most flexible processing platform you could hope to add to your collection, capable of adapting to whatever your project requires. Unlike other Single Board Computers, Arty isn't bound to a single set of processing peripherals: One moment it's a communication powerhouse chock-full of UARTs, SPIs, IICs, and an Ethernet MAC, and the next it's a meticulous timekeeper with a dozen 32-bit timers. Additionally, with the universally popular expansion headers (Arduino™ R3 Headers and our Pmod™ headers), Arty will become the most adaptable tool in your project toolbox.

can-ps7-xilinx

Xilinx Zynq CAN PS driver for ZED board.

cec-esterel

Columbia Esterel Compiler

cms-calo-layer1

Xilinx Microblaze Projects for RCT Upgrade

codesourcery

ZYNQ交叉编译工具链

connect-6-fpga

connect 6 using microblaze on fpga

designing-a-custom-axi-slave-peripheral

A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools

device-tree-xlnx

Linux device tree generator for the Xilinx SDK (Vivado > 2014.1)

device_xylon_zynqxylon

Android 4.x board support package for Xilinx Zynq boards with logi3D

digilent_zybo_fpga_train_game

Game using touch screen implemented to FPGA.

dvi2vga_lap

The 1280x720 60P image of input from the HDMI input of ZYBO in real time and then output to the VGA terminal by Laplacian filter processing.This is a project of Vivado 2015.2.

edxcel_old

Ed25519 Hardware acceleration for Zynq

ethernet-fmc-zynq-gem

Example design for the Ethernet FMC using the hard GEMs of the Zynq

finance.americanoption.zynq.hls

firmware

Firmware for MicroBlaze softcore

fpga

This repository holds all the projects and docs relating to our work with the Xilinx Zynq 7000 series FPGAs.

fpga-soc-linux

FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian8 Images (for Xilinx:Zynq-Zybo Altera:de0-nano-soc)

fpga_video

Manipulation of HDMI video with MicroBlaze. Xilinx Spartan 6.

fpgamag

FPGAマガジン向け Vivadoプロジェクト

fpgamake

Generates Makefiles to synthesize, place, and route verilog using Vivado

fpgaopencv

Проект обработки видео на FPGA Zynq с аппаратной реализацией OpenCV алгоритмов с помощью Vivado HLS

freertos-lwip-vivado-2016

FreeRTOS/lwIP (XAPP1026) for Xilinx Zynq devices using Vivado 2016. This port is compatible with Xilinx Vivado 2016 and was tested on the boards Zedboard and RedPitaya, but should work on a Xilinx ZC702 board also.

general-zynq

A general-design version of zynq

hdl