honorpeter / altera-fpga-implementation-of-fir-averaging-filter-hardware-accelerator-audio-codex Goto Github PK

This project forked from jeffjosephsen/altera-fpga-implementation-of-fir-averaging-filter-hardware-accelerator-audio-codex

The purposes of this laboratory assignment was to investigate the audio coder/decoder (CODEC) on the DE1-SoC Development Board and to utilize the CODEC in the implementation of an Finite Impulse Response Averaging Filter of 8 and N samples. The implementation of these algorithms and their testing were completed both in software on Quartus Prime Lite Edition with data verification testing in ModelSim and in hardware on the Field Programmable Gate Array (FPGA) side of the Cyclone V chip of the Altera DE1-SOC development board with the data verification testing by SignalTap II Logic Analyzer. Significant amounts of debugging occurred during the completion of the lab. Significant amounts of time were spent in debugging efforts to make the software tools and SystemVerilog code work correctly. At the end of the laboratory assignment all parts of the software and hardware worked correctly. This was demonstrated to Teaching Assistant Staff.