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100days

100 days of algorithms

18742-project

5-stage-pipeline-cpu-in-mips-architecture

acc-runtime

acc_scheduling

accelator_conv

Accelator for conv on FPGA

aes_accelerator_iot_camera_demo

AES Accelerator IoT Camera Demo

ai_project

AI Image Categorization project

altera-fpga-implementation-of-fir-averaging-filter-hardware-accelerator-audio-codex

The purposes of this laboratory assignment was to investigate the audio coder/decoder (CODEC) on the DE1-SoC Development Board and to utilize the CODEC in the implementation of an Finite Impulse Response Averaging Filter of 8 and N samples. The implementation of these algorithms and their testing were completed both in software on Quartus Prime Lite Edition with data verification testing in ModelSim and in hardware on the Field Programmable Gate Array (FPGA) side of the Cyclone V chip of the Altera DE1-SOC development board with the data verification testing by SignalTap II Logic Analyzer. Significant amounts of debugging occurred during the completion of the lab. Significant amounts of time were spent in debugging efforts to make the software tools and SystemVerilog code work correctly. At the end of the laboratory assignment all parts of the software and hardware worked correctly. This was demonstrated to Teaching Assistant Staff.

approxiamte_computing_cnn

armnn

Arm NN ML software

backup

bigpulp

RISC-V manycore accelerator for HERO, bigPULP hardware platform

bigpulp_zcu102

port of bigpulp to zcu102 board

binarynncompiler

An Automatic RTL Compiler for Deep Neural Networks Accelerator with FPGA

c3n2

Clever and Complete Convolutional Neural Network (C3N2) is a complete implementation of Lenet, including both the training and inference layer, on the Xilinx Zynqboard FPGA. The layers are implemented in High Level Synthesis (HLS)

caffe

Caffe: a fast open framework for deep learning.

caffe-deepcompression

Deep Compression follows a pipeline procedure involving Pruning, Quantization and Huffman Coding to compress deep neural network models sizes by 35x-40x. We implemented (pseudo) pruning similar to the first stage of the pipeline on LeNet-5 and decreased it's download bandwidth by 65% (after (tensorlfow) quantization & gzip compression).

caffe-in-zynq

caffe-int8-convert-tools

caffe-model-zoo

caffe pretrained models and prototxt

caffe-ssd

caffe2_fpga

Caffe2 with Xilinx Zynq support

caffezynqfpga

carnd-lenet-lab

Implement the LeNet deep neural network model with TensorFlow.

chaidnn

HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs

chainer-ssd

Implementation of SSD (Single Shot MultiBox Detector) using Chainer

cmabuf

Linux device driver for dma buffer using dma_alloc_coherent()

cmsis_5

CMSIS Version 5 Development Repository

cnn