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Common SystemVerilog components
License: Other
Shell 0.61%
C++ 1.19%
C 0.06%
Tcl 1.44%
SystemVerilog 95.29%
Stata 1.14%
Makefile 0.28%
common_cells's Introduction
๐จโ๐This is Hilbert (Yuang),
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๐ A first-year Ph.D. Student hacking Computer Systems and Architecture @ CMU.
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๐ Prior B.S. in CS @ UMich and B.E. in CE @ SJTU.
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๐ฎ An Arch Linux and Emacs user & Rustacean ๐ฆ.
- Kernel Memory Management
- Convex Optimization
- Barista Craft โ
common_cells's People