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FPGA based USB 2.0 high speed audio interface featuring multiple optical ADAT inputs and outputs

License: Other

Python 98.17% Shell 0.38% Makefile 0.36% Assembly 0.43% C 0.67%
audio fpga

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adat-usb2-audio-interface's Issues

Incompatible with latest amaranth version

Issue

2 Months ago many of the "compat" classes were removed from amaranth with this commit: amaranth-lang/amaranth@9d4ffab
Therefore, the audio interface is failing to build with various places still using the compat parts.
For instance starting with i2c from amlib which is using MultiReg:
https://github.com/amaranth-farm/amlib/blob/main/amlib/io/i2c.py#L12

Workaround

I am able to build the gateware with these revisions of amaranth and amaranth-soc:
git+https://github.com/amaranth-lang/amaranth.git@597b1b883924d8949061b52270eb55b97a7cfb76
git+https://github.com/amaranth-lang/amaranth-soc.git@87ee8a52d07a2f85b05a04db84644dce48fdfa23

Fixing

I hope this project is still paused and not abandoned ;) If it is abandoned (along with amaranth-boards, amlib, usb2-highspeed-core) let me know, so I will probably continue working on this in my own forks. Otherwise, I will try to help fixing the references, but might need some help/hints. It would be a shame if this amazing codebase gets so outdated that it cannot be built in the future anymore.
Thank you!

USB interface

Hello,
I like this project and would like to reproduce it with qmtech spartan 6 board.
Can I use USB3300 for USB interface or is there some special feature of 3320 being used?

If so, don't you happen to have one extra unpopulated PCB to sell?

Thank you.

Port to LUNA board

Would it be possible to port this to the LUNA board?

The 8 in and out optical ports should fit comfortably on one of the two available PMOD connectors (though power draw may become an issue), and the two DACs on the other.

Board exceeds JLCPCB capabilities

Got this message from JLCPCB and they cancelled my order:

"After marking the hole compensation of the original 0.4/0.6 mm, the minimum hole distance is only about 0.17 mm, and the minimum hole distance line is only about 0.08, which exceeds our capabilities. (the minimum hole distance of different networks must be greater than 0.33 mm , the hole distance line must be greater than 0.23 mm)"

I did notice that the visa and tracks were awfully close to each other, but i figured you had submitted this to JLCPCB before so i didn’t think it was an issue.

I’d do this myself, but modifying this design to fix this issue messes with it far more than I am comfortable with.

the full list of capabilities can be found here: https://jlcpcb.com/capabilities/Capabilities

S/PDIF support?

I realize that S/PDIF is a different protocol and may take some effort to work because of variable clock speeds, but is this something that you are thinking about implementing in the future?

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