Complete ASIC Flow of I2C Communication Protocol

Project Overview

This project involves the complete ASIC flow for designing an I2C communication protocol. The I2C (Inter-Integrated Circuit) protocol is a multi-master, bi-directional serial bus, designed to facilitate efficient data exchange between devices over short distances. It is particularly useful for applications requiring occasional communication among multiple devices.

This project was conducted as part of the Advanced Digital Design course (CND 211) under the supervision of the CND Team at AUC. The objective was to create a complete layout (GDS) of an I2C protocol using the provided PDK under nominal supply conditions.

Project Description
Tasks Performed
Assessment Criteria
Directory Structure
Setup and Usage
Contributors

Project Description

The I2C protocol is a robust standard for short-distance communication between devices. It includes features like multi-master capability, collision detection, and arbitration to prevent data corruption. The design process for this project followed the standard ASIC flow, encompassing synthesis, verification, timing analysis, floorplanning, power planning, clock tree synthesis, placement and routing, and the final layout design.

Tasks Performed

Synthesis of the Code: Conversion of the high-level design into a gate-level representation.
Formal Verification: Ensuring the synthesized design matches the high-level specification.
Static Timing Analysis: Verifying the timing of the design to ensure it meets required constraints.
Creating the Floorplan and Power Plan: Defining the layout and power distribution for the design.
Clock Tree Synthesis: Designing the clock distribution network to ensure proper timing.
Placing and Routing the Core: Physically placing the components and routing the connections.
Design and Layout of the Pad Ring: Designing the interface for inputs and outputs.
Signoff and Final Complete Layout: Final verification and preparation of the layout for fabrication.

Assessment Criteria

The project was assessed based on the following criteria:

Synthesis of the code
Performing static timing analysis
Performing Formal Verification
Creating the floor plan
Creating the power plan
Performing clock tree synthesis
Placing and routing
Design and layout of the pad ring with all the required inputs and outputs
Signoff and final complete layout

Directory Structure

.
├── docs/                 # Documentation files
├── src/                  # Source files for I2C design
├── synthesis/            # Synthesis reports and scripts
├── verification/         # Formal verification files and reports
├── timing_analysis/      # Static timing analysis reports
├── floorplan/            # Floorplanning files and scripts
├── power_plan/           # Power planning files and scripts
├── clock_tree/           # Clock tree synthesis files
├── place_and_route/      # Placement and routing files and reports
├── pad_ring/             # Pad ring design files
├── signoff/              # Final layout files and signoff reports
└── README.md             # This readme file

Setup and Usage

Clone the repository:

git clone https://github.com/habibhossam/Complete-ASIC-Flow-of-I2C-communication-protocol.git
cd Complete-ASIC-Flow-of-I2C-communication-protocol

Environment Setup: Ensure you have the necessary tools installed for ASIC design, including synthesis, verification, and timing analysis tools. Consult the docs/setup.md for detailed setup instructions.
Running the Flow: Each major step in the ASIC flow has corresponding scripts and instructions in its directory. Follow the README files within each directory for step-by-step instructions.
Generating the Final Layout: After performing all the steps, the final layout (GDS) can be found in the signoff directory. This file is ready for fabrication.

Contributors

Habib Hossam - GitHub
Adham Mohamed - GitHub
Mohamed Abouelhamd - GitHub
Tarek Omara - GitHub
Abdallah Yehia - GitHub

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