habibhossam Goto Github PK

-fifo-testbench

verify a FIFO design based on the provided RTL code “FIFO.v”

4-bits-full-adder

The aim of this project is to design 4-bit Full Adder using different techniques (Ripple Carry, Carry LookAhead)

complete-asic-flow-of-i2c-communication-protocol

design-and-optimization-of-fully-differential-discrete-time-2nd-order-sigma-delta-adc

In this project, we aim to design and optimize a fully differential sigma-delta ADC that achieves exceptional performance in terms of noise shaping, signal-to-noise ratio (SNR), and bandwidth.

design-of-an-rf-front-end-of-a-receiver-chain

design and simulate the LNA and Mixer blocks independently to ensure their individual functionality. Subsequently, the two blocks are integrated and simulated together to validate their combined functionality and performance within the receiver chain

design-spartan6---dsp48a1-using-vivado

Using Vivado to go through the design flow running elaboration, synthesis, implementation for all the designs making sure that there are no design check errors during the design flow..

full-custom_sdes

The primary objective of this project is to design and implement a Simplified Data Encryption Standard (S-DES) algorithm, which retains the essential features of the DES algorithm but with much smaller parameters.

fully-integrated-folded-cascode-ota-with-common-mode-feedback-network

Design Steps, Simulation, Analysis, and Layout verification of a Fully Integrated Folded Cascode OTA with Common mode feedback network using UMC 65nm technology

graduation-project

Graduation Project

habibhossam

Config files for my GitHub profile.

microprocessor-design

Microprocessor Design like SAP-1

object_detection_model_for_smart_blind_stick

Object Detection Deep Learning Model for Smart Blind Stick

spi-slave-with-single-port-ram

Designing SPI Slave with Single Port RAM using questasim and vivado.

verification-of-spi-slave-ip-with-systemverilog