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Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.

Home Page: https://www.airisc.de

License: Other

Makefile 3.04% Tcl 16.99% Verilog 57.53% SystemVerilog 12.56% C 9.42% Assembly 0.39% GDB 0.01% Shell 0.06%
risc-v riscv fpga verilog embedded-systems ai asic smart-sensors asil functional-safety

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crolfes avatar stnolting avatar stnolting-ims avatar utz12 avatar

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airisc_core_complex's Issues

License (file) issue

This project is licensed under the "Solderpad Hardware License v2.1" license, but the LICENSE file provides custom additions making it a "nonstandard" version of the license. Furthermore, GitHub and integration tools cannot identify this modified license file:

license

This also prevents GitHub from showing the project license in the "About" tab on the right side.

I suggest to revert the LICENSE file to the original text of the Solderpad Hardware License v2.1 and add custom extensions as LICENSE.addon.md or note them in the front-page README.

BlockRAM configuration issue

I'm trying to synthetize, implement and generate the bitstream for the NexysVideo board.

Firstly, I tried to do it manually following the instructions on the user guide . It worked but if I try to simulate the top level design with the test bench all the tests fail.

Then I did the same using the tcl script and the Makefile, everything worked fine and all the tests have passed. I found out that the only differences betweeen the two project created are the options in the BlockRAM that the user guide says to set as:

Generate address interface with 32 bits : yes
Common Clock                            : no

while the xcix file contains them set as:

Generate address interface with 32 bits : no
Common Clock                            : yes

In deed if I change the options as the latter the TB passes. Is there a problem with the TB or the configuration specified in the user guide is wrong ?

The image below shows the errors I obtain when executing the TB using 32 bit address interface and no common clock.
vivado-error

Missing modules when enabling some ISA extensions

Hello,
I'm trying to generate the bitstream of the AIRISC core for a Nexys4 DDR board.
The application that I would like to run on this board is an AI one and I was thinking about using some extensions to speed it up.

Now, in the airi5c_arch_options.vh file there are some extensions that when defined give errors in synthesis.
Those are: ISA_EXT_AIACC that don't find the airi5c_ai_acc module and also ISA_EXT_P for the SIMD extension saying that module airi5c_mul_div_simd is missing

Would it be possible to fix ?

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