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add scan chain during the synthesis
from the tft labs

11. Optimize power consumption from an architectural point of view (OP-
    TIONAL) Improve performance using: Parallelizing, pipelining, Feedback, Clock
    Gating, Isolation...

7. Instructions subset (RECOMMENDED) The following instructions (a subset
   or all of them) could be added in order to achieve pro functionality:
   addu, addui, jalr, jr, lb, lbu, lhi, lhu, sb, seq, seqi, sgeu, sgeui, sgt, sgti, sgtu, sgtui, slt,
   slti, sltu, sltui, sra, srai, subu, subui, mult (using integer registers: something should
   be modified).

8. Data path (OPTIONAL) The data path can be extended for each of the instruction
   you choose to add. Furthermore, independently from the instruction, try to optimize
   the microarchitecture so that the critical path is reduced (e.g. for the ALU you can
   choose one or more of the arithmetical structures analysed during lectures or suggested
   by the teacher.

Physical design (OPTIONAL) Post physical design simulations, clock tree syn-
thesis and even crosstalk analysis would be appreciated in the final report.

these instructions can be meaningfully checked. Change the ALU OPCODE so that
an enumeration type can be used (see appendices A and B).

Caching (OPTIONAL) Add a small data cache (RTL) between the main mem-
ory and the CPU; define type of association, a coherency policy and a replacement
strategy. (Of course the CU must be updated accordingly)

implement an empy datapath

scripts, results and reports is due together with all the code. Remember that a report
is an important aspect of a project: it let one know how detailed was your work and
how to use it. This will be evaluated as well.

Whatever you want not mentioned before... (FUNDAMENTAL) Feel you
FREE to add features to your personal DLX!

Control hazard (OPTIONAL) Implement one or more of the techniques to prevent
stall as mentioned during classes as instruction queue for jump (IQ), branch prediction
using a small branch history table.

level all the data path components necessary to fulfill the instruction subset defined
at previous points. Of course you can reuse the blocks you already described in
previous labs. Describe one or more intelligent assembler programs (COMMENTED)
so that these instructions can be meaningfully checked.

Synthesis
Physical Design

Post physical design performance must be reported: delay, EM, thermal informa-
tions, power... before and after optimization steps. (Follow what you learn in the
labs.)

Advanced synthesis (OPTIONAL) Force further optimization to the design: try
to reduce power consumption, perform a post synthesis VHDL simulation, so that
realistic timing and power simulation with a real test bench can be performed (you
will ask suggestions on this points).

Different synthesis results can be reported. A final optimization for frequency must be
performed. The scripts you use for the synthesis step must be reported and commented
(memory should not be synthesized).

Windowing (OPTIONAL) Use the windowed register file to support routine con-
text switching and complete the control unit to support it.