franout / dlx_project

Deluxe RISC processor

DeLuXe RISC processor project

RISC processor architecture designed by John L. Hennessy and David A. Patterson.

Microelectronic System course (MsC in Embedded Systems Engineering) @ Polythecnic of Turin, Italy

Table of Contents

• Setup
• Architecture
• Software
• Simulation
• Synthesis
• Layout
• Tests
• Documentation
• License

Clone

Clone this repo to your local machine using and feel free to contribute!

$ git clone https://github.com/franout/DLX_project.git

Setup

You need to have installed a HDL simulator tool (for the simulation) and a synthesis tool (in case you want to synthesize the design). In this project Questa Sim 10.7 and Design Compiler have been used.

Architecture

The DLX is essentially a cleaned up (and modernized) simplified MIPS CPU. The DLX has a simple Big Endian 32-bit load/store pipelined architecture, somewhat unlike the modern MIPS CPU.

• DLX top level entity

• Customizable hardware parameters (pre-synthesis)

  • IR size, bitwidth of Instruction Register
  • PC size, bitwidth of Program Counter

Software

For creating creating the hex dump file to be used in the simulation (loaded in the Instruction Data Ram):

  $ ./software/assembler.sh {ASM_FILE_PATH}

The produced hexadecimal file should be copied in the memories folder.

Moreover, in the memories folder it is present also a python script for generating random data suitable for the DRAM.

  $ ./hardware/dlx/test_bench/memories/generate_random_values_dram.py

Simulation

For exectuting the simulation of the DLX, it is necessary to execute:

  $ ./scripts/simulation.sh

It will compile the needed files for executing the simulation. Moreover, there are two types of simulations, one with the Universal Verification Methodology architecture and the other one with the normal configuration (IRAM-DLX-DRAM).

Synthesis

For executing the synthesis of the DLX:

  $ ./scripts/synthesis.sh

It will execute different synthesis with different clocks (starting from unconstrained design) and area footprint. Moreover, it will be synthesized taking into account a possible Scan chain (DfT) for a further production phase.

Layout

For executing the physical design of the synthesized DLX:

  $ ./scripts/physical_design.sh gui/no_gui

It will execute the physical desing of differt design point ( for different clock values and area).

Tests

For functionally verify the microprocessor refers to the testbench in System Verilog. They are divided for each stage and control unit for regression test

  $ ./scripts/regression_test.sh

Documentation

For a more detailed information see Wiki's project.

Useful Link

Reach out to me at one of the following places!

• System Verilog Tutorial
• System Verilog Tutorial 2
• Model Sim User Manual
• Overflow of binary numbers
• Universal Verification Methodology tutorial

License

GNU General Public License v3.0

dlx_project's Issues

Design for testabiity

add scan chain during the synthesis
from the tft labs

b - instruction subset

pro

11. Optimize power consumption from an architectural point of view (OP-
    TIONAL) Improve performance using: Parallelizing, pipelining, Feedback, Clock
    Gating, Isolation...

Design modify and COMMENT one (or more) intelligent assembler programs so that

these instructions can be meaningfully checked. Change the ALU OPCODE so that
an enumeration type can be used (see appendices A and B).

pro

Control hazard (OPTIONAL) Implement one or more of the techniques to prevent
stall as mentioned during classes as instruction queue for jump (IQ), branch prediction
using a small branch history table.

Architectural design of DLX processor

implement an empy datapath

pro

Caching (OPTIONAL) Add a small data cache (RTL) between the main mem-
ory and the CPU; define type of association, a coherency policy and a replacement
strategy. (Of course the CU must be updated accordingly)

Report (MANDATORY) A final report describing your design, your code, your

scripts, results and reports is due together with all the code. Remember that a report
is an important aspect of a project: it let one know how detailed was your work and
how to use it. This will be evaluated as well.

pro

8. Data path (OPTIONAL) The data path can be extended for each of the instruction
   you choose to add. Furthermore, independently from the instruction, try to optimize
   the microarchitecture so that the critical path is reduced (e.g. for the ALU you can
   choose one or more of the arithmetical structures analysed during lectures or suggested
   by the teacher.

pro

Physical design (OPTIONAL) Post physical design simulations, clock tree syn-
thesis and even crosstalk analysis would be appreciated in the final report.

Documentation

memories design and tb

very fucking fancy testbench in sv

pro

Advanced synthesis (OPTIONAL) Force further optimization to the design: try
to reduce power consumption, perform a post synthesis VHDL simulation, so that
realistic timing and power simulation with a real test bench can be performed (you
will ask suggestions on this points).

Physical design (BASIC) The synthesized design must be placed and routed.

Post physical design performance must be reported: delay, EM, thermal informa-
tions, power... before and after optimization steps. (Follow what you learn in the
labs.)

Data path (MANDATORY) You should describe in VHDL (or Verilog) at RT

level all the data path components necessary to fulfill the instruction subset defined
at previous points. Of course you can reuse the blocks you already described in
previous labs. Describe one or more intelligent assembler programs (COMMENTED)
so that these instructions can be meaningfully checked.

B- pipeline

pro - reccomendedd

7. Instructions subset (RECOMMENDED) The following instructions (a subset
   or all of them) could be added in order to achieve pro functionality:
   addu, addui, jalr, jr, lb, lbu, lhi, lhu, sb, seq, seqi, sgeu, sgeui, sgt, sgti, sgtu, sgtui, slt,
   slti, sltu, sltui, sra, srai, subu, subui, mult (using integer registers: something should
   be modified).

pro

Windowing (OPTIONAL) Use the windowed register file to support routine con-
text switching and complete the control unit to support it.

Synthesis (BASIC) Both the data path and the control unit must be synthesized.

Different synthesis results can be reported. A final optimization for frequency must be
performed. The scripts you use for the synthesis step must be reported and commented
(memory should not be synthesized).

synthesis, simulation and physicall desing script

Simulation & Benchmarking

Synthesis
Physical Design

pro pro pro

Whatever you want not mentioned before... (FUNDAMENTAL) Feel you
FREE to add features to your personal DLX!

readme file

uvm

debug core

vv top level