csail-csg / riscy-ooo Goto Github PK

I can't install the Bluespec compiler, because the version is too old. I used BSC instead of. However, i can't find the ddr3 ip .v. Because you have the two steps.
$ cd $RISCY_HOME/fpgautils/xilinx/vc707/ddr3_1GB_bluespec
$ ./copy_verilog.sh
Finally, i have to say i want to run riscy ooo based on vc707 board.

Hi @sizhuo-zhang,

I see the following error when I boot F1 with (riscv-pk/bbl and rom_core_1). Have you experienced this before?

ubuntu@ip-192-168-0-207:~/riscy-OOO/procs/build/RV64G_OOO.core_1.core_SMALL.cach
e_LARGE.weak.l1_cache_lru.check_deadlock/awsf1/bin$ ./ubuntu.exe --core-num $N --mem-size 2048 --ignore-user-stucks 1000000 --rom rom_core_$N --elf bbl
subprocess pid 8767 completed status=0 0
[initPortalHardwareOnce:284] fd 6 len 0
[checkSignature:176] read status from '/dev/connectal' was only 0 bytes long
checkSignature: driver 'pcieportal.c' signature mismatch 9a4e6520472c69f1577083d9f60b826c 47e961a4b445762e6b6024086a3ff16b
[checkSignature:170] failed to open /dev/portalmem No such file or directory
./ubuntu.exe: symbol lookup error: ./ubuntu.exe: undefined symbol: _Z8load_elfPKcP7memif_tPm

Any pointers would be greatly helpful.
Thanks!

Hi,

I just want to confirm that make target hw/mkTop.bit is a part of synthesis flow only for fpga boards (eg. zedboard, vc707 etc) and not for awsf1, right?.

Thanks!

The JALR and branch instructions have redundant encodings in their funct3 fields that are illegal. Based on my reading of the spec: for JALR, only 3'b000 is legal, and for branches, 3'b010 and 3'b011 are illegal. These cases aren't addressed in decode:

For JALR, this leads to it having 8 encodings that all behave identically. For branches, presumably the case gives an undefined result, which hopefully defaults to one of the other legal cases.

This came up as I was fuzzing and wasn't getting a trap on 0x0000a267: a JALR but with 3'b010 instead of 3'b000 in the funct3 field.

I'd be happy to make a PR to fix this if I've identified the issue correctly.

Kindly clarify the below mentioned issues:

1. For RV32G variant, I want to find how many CPU cycles are required for execution of each instruction

I have searched a lot to find out that how many clock is needed for operation of each instruction in ISA RV32G variant, but I couldn’t find any thing.

2. The base timing information is required for RV32G variant for determining the CPU cycle time. Can anyone Kindly suggest the information in this regard

Thanks in advance

The makeSystemConsistent call in the CommitStage:

This may prevent TLB entries sticking around across context switches if working sets are small, hurting performance, and will also require two consecutive flushes in the common case of changing SATP and calling sfence.VMA in short succession.