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2-way-set-associative-cache-controller

Synthesizable and Parameterized Cache Controller in Verilog

4-way-set-associative-cache-verilog

Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy

4way-cache

Verilog cache implementation of 4-way FIFO 16k Cache

adv_dbg_if

Universal Advanced JTAG Debug Interface

ahb3lite_interconnect

AHB3-Lite Interconnect

ahb3lite_memory

Multi-Technology RAM with AHB3Lite interface

ahb3lite_pkg

Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces

ahb3lite_timer

RISC-V compliant Timer IP

apb4_gpio

General Purpose IO with APB4 interface

ariane

Ariane is a 6-stage RISC-V CPU capable of booting Linux

cores-swerv

SweRV EH1 core

darkriscv

opensouce RISC-V implemented from scratch in one night!

e200_opensource

The Ultra-Low Power RISC Core

eecs470-proc

Out-of-Order processor design

hamming-ecc

Hamming ECC Encoder and Decoder to protect memories

hbird-e-sdk

The software development kit for Hummingbird E200 Series RISC-V Core and SoC platform

hier-icache

ibex

Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

memory

Generic memory implementations

nyuziprocessor

GPGPU microprocessor architecture

nyuzitoolchain

Port of LLVM/Clang C compiler to Nyuzi parallel processor architecture

openc910

OpenXuantie - OpenC910 Core

plic

Platform Level Interrupt Controller

pulp

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

rars

RARS -- RISC-V Assembler and Runtime Simulator

ridecore

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

riscv

RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU

riscv-boom

BOOM: Berkeley Out-of-Order Machine

riscv-cores-list

RISC-V Cores, SoC platforms and SoCs

riscv-debug-spec

Working Draft of the RISC-V Debug Specification Standard