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If the rounding mode is set to round up, fcvt.wu.d of a denormalized value rounds down to zero rather than rounding up to 1. (Spike gets this right).

Here's a test:

.global _start
_start:
lui ra, 2
csrs mstatus, ra

_test:
li t0, 0x10
fmv.d.x f1, t0
fcvt.wu.d a0, f1, rup

Hi all,

I don't know if it is only with my gcc version 11.1.0 but I am getting the next error when I tried to use the elf_to_hex.c file to compile with the Makefile in Tests/elf_to_hex.

The error:

gcc -g -o elf_to_hex  elf_to_hex.c  -lelf
/tmp/cc4D9tPQ.o: in function `c_mem_load_elf':
/home/jairom/Documents/TUD_Projects/05_Semester/Piccolo/Tests/elf_to_hex/elf_to_hex.c:94:(.text+0x25a): relocation truncated to fit: R_X86_64_PC32 against symbol `bitwidth' defined in .bss section in /tmp/cc4D9tPQ.o
/home/jairom/Documents/TUD_Projects/05_Semester/Piccolo/Tests/elf_to_hex/elf_to_hex.c:98:(.text+0x2a2): relocation truncated to fit: R_X86_64_PC32 against symbol `bitwidth' defined in .bss section in /tmp/cc4D9tPQ.o
/home/jairom/Documents/TUD_Projects/05_Semester/Piccolo/Tests/elf_to_hex/elf_to_hex.c:130:(.text+0x394): relocation truncated to fit: R_X86_64_PC32 against symbol `min_addr' defined in .bss section in /tmp/cc4D9tPQ.o
/home/jairom/Documents/TUD_Projects/05_Semester/Piccolo/Tests/elf_to_hex/elf_to_hex.c:131:(.text+0x39f): relocation truncated to fit: R_X86_64_PC32 against symbol `max_addr' defined in .bss section in /tmp/cc4D9tPQ.o
/home/jairom/Documents/TUD_Projects/05_Semester/Piccolo/Tests/elf_to_hex/elf_to_hex.c:132:(.text+0x3aa): relocation truncated to fit: R_X86_64_PC32 against symbol `pc_start' defined in .bss section in /tmp/cc4D9tPQ.o
/home/jairom/Documents/TUD_Projects/05_Semester/Piccolo/Tests/elf_to_hex/elf_to_hex.c:133:(.text+0x3b5): relocation truncated to fit: R_X86_64_PC32 against symbol `pc_exit' defined in .bss section in /tmp/cc4D9tPQ.o
/home/jairom/Documents/TUD_Projects/05_Semester/Piccolo/Tests/elf_to_hex/elf_to_hex.c:134:(.text+0x3c0): relocation truncated to fit: R_X86_64_PC32 against symbol `tohost_addr' defined in .bss section in /tmp/cc4D9tPQ.o
/home/jairom/Documents/TUD_Projects/05_Semester/Piccolo/Tests/elf_to_hex/elf_to_hex.c:155:(.text+0x4c6): relocation truncated to fit: R_X86_64_PC32 against symbol `min_addr' defined in .bss section in /tmp/cc4D9tPQ.o
/home/jairom/Documents/TUD_Projects/05_Semester/Piccolo/Tests/elf_to_hex/elf_to_hex.c:156:(.text+0x4d6): relocation truncated to fit: R_X86_64_PC32 against symbol `min_addr' defined in .bss section in /tmp/cc4D9tPQ.o
/home/jairom/Documents/TUD_Projects/05_Semester/Piccolo/Tests/elf_to_hex/elf_to_hex.c:157:(.text+0x4f3): relocation truncated to fit: R_X86_64_PC32 against symbol `max_addr' defined in .bss section in /tmp/cc4D9tPQ.o
/home/jairom/Documents/TUD_Projects/05_Semester/Piccolo/Tests/elf_to_hex/elf_to_hex.c:158:(.text+0x515): additional relocation overflows omitted from the output
collect2: error: ld returned 1 exit status
make: *** [Makefile:7: elf_to_hex] Error 1

The problem can be solved adding the the flag -mcmodel=medium. According to what I have read is because this particular C file requires a large amount of memory in the stack that could not be fulfilled using a 32 bits AS operations. Is this a unique problem from my environment?

Thank you for your time,

Jairo M

With Piccolo, nmsub.s with rounding mode=RNE and all the source registers containing IEEE positive zero returns an IEEE negative zero.

I believe that the correct IEEE 754:2008 result is negative zero if the rounding mode is RDN, and positive zero otherwise. Spike gives the result I expected.

Here's a test:

.global _start
_start:
lui ra, 2
csrs mstatus, ra
fmv.w.x ft0, zero

_test:
fnmsub.s ft0, ft0, ft0, ft0, rne
fmv.x.w a0, ft0

Create a reference TCA which uses the custom instruction support in the CPU to receive commands. The TCA needs to support operations which have both scalar and vector results.

Hi I'm trying to port dhrystone benchmark on RV32m1 Vegaboard i have downloaded the source code of dhrystone from
https://github.com/TWilmer/dhrystone and im using eclipse ide can somebody please tell me how to build a project and port the dhrystone on vegaboard

Add macros for using custom instructions. Refer:

https://github.com/riscv/riscv-gnu-toolchain/issues/190

Verify support for custom instructions in RV toolchain.

Hello to people maintaining the project, I would like to contribute to this amazing hardware project and I was wondering if this project can be taken to google summer of code 2021, the organization application openings start from February I believe, please do consider my request.

Since the MMU Cache shifts the memory access result based on the alignment of the address request, and the 1 to indicate SC failure is passed through the same logic, the 1 is shifted out in the case that the address is misaligned, leaving 0 which falsely indicates success.

Example code sequence:
auipc a0, 0x0
addi a0,a0,52 # load 4-byte but not 8-byte aligned value into a0
li a1, 42 # arbitrary value to be stored
sc.w a2, a1,(a0) # perform an SC that should fail (no paired LL)

Piccolo RV32ACIMU currently returns 0 in this case.

fcvt.wu.s of negative zero of IEEE negative zero sets FCSR.NV, Spike doesn't set the flag. I believe that what spike does is the correct IEEE 754:2008 behaviour.

Here's a test:
.global _start
_start:
lui ra, 2
csrs mstatus, ra
fmv.w.x ft0, zero
test:
fsgnjn.s f0, f0, f0
fcvt.wu.s t0, f0, rtz
csrrs a0, fcsr, zero

When you have a branch instruction with an illegal funct3 field (e.g. 3'b010), the processor triggers an exception and jumps to the exception handler, but it sets the wrong cause to the mcause CSR. The cause should be illegal instruction (2) instead of instruction address misaligned (0). I haven't looked to see if there are any other illegal instructions that result in the wrong cause to be written to the mcause CSR.

The relevant code in Piccolo can be found here: https://github.com/bluespec/Piccolo/blob/master/src_Core/Core/EX_ALU_functions.bsv#L227-L239

And here is a small test I used to observe the error:

.text.init:

.globl _start
.globl tohost
.globl exit

_start:
    # setup trap handler
    la t0, trap_handler
    csrw mtvec, t0
    # do an illegal instruction that looks like a branch
    .word 0x00002063
    # .word 0x00001063 # legal branch
    li a0, 1337
    j write_tohost

trap_handler:
    csrr a0, mcause
    j write_tohost

write_tohost:
    slli t0, a0, 1
    ori t0, t0, 1
    la t1, tohost
    sw t0, 0(t1)
exit:
    j exit

.align 4

tohost:
    .word 0x0

This test prints PASS when it runs because the mcause CSR had 0 in it (the code for instruction address misaligned). This test should fail with a code of 2 representing an illegal instruction exception.

When you set the verbosity of the CPU to be 1 or 2, the verbosity of the MMU_Cache.bsv file is stuck-at-0. Hence, none of the display messages of this file can be displayed during simulation. This can be verified by running any isa test with VERBOSITY=+v1 or VERBOSITY=+v2 and checking the output log.

I believe the problem is that although MMU_Cache.bsv has a set_verbosity method, there is no way to reach it as the Near_Mem_IFC.bsv file doesn't have one.

One possible solution is to add set_verbosity method to the Near_Mem_IFC.bsv file (with a proper body in Near_Mem_Caches.bsv) and call it in the set_verbosity method of the CPU.bsv file.
https://github.com/bluespec/Piccolo/blob/master/src_Core/Core/CPU.bsv#L1477-L1480

Thank you

Hi, I hope you are well.

What is Piccolo's L1 cache replacement policy? Which bus is activated when a cache flush/eviction happens?

Also, is it possible to generate a Piccolo version with cache sizes smaller than 1KB (say 256/512 bytes)? I am asking because it seems like I can't have a value < 1 here in the kb_per_cache

Thanks!

Simply from reading the code at https://github.com/bluespec/Piccolo/blob/master/src_Testbench/Fabrics/AXI4/AXI4_Deburster.bsv#L174 (understand "I have not tested what I am about to claim in any way"), it looks to me like a single write request may receive many write responses. Maybe it does not really matter if in practice those responses are ignored, but I presume that this is in general undesirable?
Or am I simply missing something?

Dispatch an instruction with a custom opcode to a TCA, and collect the response.

• Stage1 modification to detect a custom instruction
• Dispatch custom instruction to TCA from Stage2
• Collect responses from TCA in Stages 2 and 3
• Service memory read and write requests from TCA

Execution of
$make simulator

in the
builds/<ARCH>_<CPU>_verilator/

directory results in
%Warning-DEPRECATED: Verilog_RTL/mkTop_HW_Side_edited.v:7: Deprecated -msg in configuration files, use -rule instead.

%Error: Exiting due to 6 warning(s) make: *** [../../builds/Resources/Include_verilator.mk:52: simulator] Error 1

How to resolve this error?

I see an impressive 1.9 DMIPS/MHz performance reported here for the RV32IM version of Piccolo. I'm interested in reproducing this result as well as study the effect of different configurations. I would also be interested in CoreMarks figures as a better alternative. Are ports of Dhrystone/CoreMark available for Piccolo/Flute/Toooba?

As the results of these tests are usually printed on the console:
Are there any documentation/examples available for using the available UART? Do I only need to store at address '0xc0000000' ? Is there a libgloss port or even simple a printf wrapper available?

Hi,
when I run DC of the BRVF_Core project, it occurs the Error that is "BRAM.v:99: Net 'RAM[0][63]' or a directy connected net is driven by more than one source, and not all drivers are three-state".
Does the BRAM.v have bug or I set somewhere wrong?
best wishes!

Here's a test case:

_start:
lui ra, 2
csrs mstatus, ra
_test:
li t0, 0x40e6a09e66689b2e
fmv.d.x f0, t0
fcvt.w.d a0, f0, rmm

Piccolo rounds down to 0xb504, while spike rounds up to 0xb505. I believe that spike is correct.

(If you're wondering where the strange constant came from, it's sqrt(MAXINT), but I think that isn't important for this bug).

This is a minor issue.

For SSITH, I may extend the source code of Piccolo (and Flute). During these early phases, I am reading and understanding the source code. I noticed some mixed (tab, spaces) or non-correct indentation that reduces the code readability. I can easily fix it on my side as I proceed with my feature integration, but it would be great to have it fixed on the baseline.

Thank you!

Hi, I hope you are well.

I want to analyse the waveforms for the execution of an elf in the /tests folder. For this purpose, I uncommented line 41 of the makefile in /builds/Resources/Include_verilator.mk. In one of the /builds/*_verilator folders, I executed the make simulator and make test commands, but I could not find where the VCD file is. Is there any other modification required that I missed?

Also, I want to analyse the L1 cache behaviour. Hence, which cache replacement policy does Piccolo use?

Hi,
Do you have the testbench or program to run the dhrystone,or the result of dhrystone by riscv-gcc?

best wishes

I recently took an opportunity to review mkFabric_AXI4.v using a formal AXI4 property checker under SymbiYosys. It appears to have some difficulties routing packets from the correct source to the correct destination. The attached (abbreviated) trace should give you an idea of what I'm talking about.

In this example, a burst packet presented from master 0 gets routed to slave 0. The associated W* channel data, however, gets corrupted in the process. (The appropriate WSTRB value sent by the master was 0, not 4.) Not shown are two similar bursts presented from master 1 during this time which may (or may not be) relevant.

Dan

Hi,
I would like to view the micro-architecture of Piccolo, and I noticed that the pdf file should be in the directory Doc/Microarchitecture/Microarchitecture.pdf according to the README. However, I could not find this directory.
So I would like to ask where the pdf file locates. Thank you so much for your time!

I tried building Piccolo as a simple RV32 IM yesterday, and the compile failed, saying:

Error: "../../src_Core/CPU/CPU_Stage1.bsv", line 243, column 35: (T0004)
  Unbound variable `instr_C'

It comes from here, where instr_C is used outside of an ISA_C block.

I'm not sure the most elegant way to handle this, but I've done this in the meantime locally and it works fine as far as I can tell:

         if (alu_outputs.exc_code == exc_code_ILLEGAL_INSTRUCTION)
`ifdef ISA_C
            tval = (is_i32_not_i16
                    ? zeroExtend (instr)
                    : zeroExtend (instr_C));                   // The instruction
`else
            tval = zeroExtend (instr);
`endif

Hi, I hope you are well.

Does Piccolo support FreeRTOS?