aucohl / lighter Goto Github PK

The SDFFE RTLIL cell is mapped to a clock gate cell + SDFF cell. Performing clock gating on this type of cells breaks the following test cases in validation:

• blake2s
• blake2s_core
• chacha
  The validation of all test cases pass when this mapping is removed.
  Thus, this mapping is removed temporarily. Power reports will show wrong results until this issue is fixed, because the power calculations presume that all flip-flops are clock-gated.

The selection implemented works only for the technology mapping, so incase only one module is selected, all modules will have operations on their memory cells, even though they will not be mapped.

The latches of the clock gates should have 1.0 activity factor.

Rather than having yet another repository which needs to be installed along with Yosys, it would be better to have this be part of the yosys-f4pga-plugins repository which contains other useful plugins like SystemVerilog support (using UHDM), SDC support, and design inspection.

This means you'll then get the benefit of being part of a bigger suite of plugins, including people to review your code, etc.

this is more over question instaed technical issue
i thought of integrate automatic clock gating in openlane's yosys.

how can i do it?
plese let me know or if u have any resources plese do share the link!

thanks in advance!!

The blake2s_core design passes validation as RTL, and normal gate level netlist, however fails validation after clock gating.