Related Issues (15)
- Blake2s_core clock gated design fails in validation HOT 1
- SDFFE mapping crashes validation HOT 2
- Make lighter PDK independent HOT 1
- Power report does not consider clock-gating cells high activity HOT 4
- Add support for other sky130 standard cell libraries. HOT 1
- Add support for other open source PDKs. HOT 2
- Move module to be part of yosys-f4pga-plugins HOT 5
- report_power.py needs to be generic HOT 1
- Move power_report_summary.csv from the root to a subfolder HOT 1
- Make the plugin selection for both techmap and memory commands HOT 1
- Add liberty file for GF180 PDK HOT 2
- can i try this in openlane's yosys. HOT 9
- Update Reports to include $SDFFE cells
- Fix all platforms' map files
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