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A pipelined MIPS microprocessor written in VHDL and simulated in Xilinx Vivado targeting Basys3 board. Simplified MIPS instruction set. Made in RIT DSD2 (CMPE-260).

VHDL 34.76% Assembly 0.69% Tcl 11.89% Verilog 6.42% SystemVerilog 46.23%
clock-speed dsd2 fpga mips processor vhdl vivado

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mips's Issues

restructure folders

change folder structure

  • eliminate nested garbage artifacts from using Vivado
  • undo organization by labs

add image

add image from Vivado, etc, to README in order to elucidate the repo purpose in addition to the README words

fix synthesis

choose correct version of files so that design is synthsizable (Ex7 version)

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