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The following property is asynchronous:

property amiq_apb_sel_validity_during_transfer_phases_p;
  @(posedge enable) disable iff(!reset_n || !en_protocol_checks) (|sel);
endproperty

It's sensitive to glitches on enable. It should be rewritten as:

property amiq_apb_sel_validity_during_transfer_phases_p;
  @(posedge clk) disable iff(!reset_n || !en_protocol_checks) (enable |-> |sel);
endproperty

The property checks that sel doesn't go down one cycle after it goes up:

property amiq_apb_sel_minimum_time_p;
  @(posedge clk) disable iff(!reset_n || !en_protocol_checks)
    $rose(|sel) |-> not(##1 $fell(|sel));
endproperty

Since what it's checking is the or reduce of sel, what is still allowed by the property is that sel changes to a different slave, but doesn't go down completely. Moreover, the not operator seems to cause problems with strong/weak semantics in certain simulators. The use of overlapping implication followed by a delay also spawns extra threads, which might cause some performance overhead. You could rewrite the assertion as:

$rose(|sel) |=> $stable(sel));

It makes more sense to drive any delay cycles for an item before actually driving that item and not afterwards.

Reasons:

1. Random delays after reset are possible out of the box, otherwise users have to insert delays themselves
2. The item is marked as finished by finish_item() when it is done

The sequencer base class has a reference to uvm_test_done, which is deprecated. This means it's not possible to compile a project using UVM_NO_DEPRECATED, unless doing a separate compile of the APB UVC which doesn't have this define set.

Not all scoreboards/coverage collectors are going to care about the access phase information. It's more difficult to throw away every first item of a pair than it is to merge a two streams from two different analysis ports, one for each item.

Since the UVC doesn't do any kind of reset at the start of the simulation (only when triggered), I need to implement drive a negedge on reset_n at time 0:

  bit reset_n = 1;
  bit clk;

  always #1 clk = ~clk;

  initial begin
    reset_n <= 0;
    @(negedge clk);
    @(negedge clk);
    reset_n <= 1;
  end

Normally I start a sequence in my test also at time 0:

virtual task run_phase(uvm_phase phase);
    apb_filter_tb::filter_sequence seq =
      apb_filter_tb::filter_sequence::type_id::create("seq", this);

    phase.raise_objection(this);

    seq.start(tb_env.master_agent.sequencer);

    phase.drop_objection(this);
  endtask

The problem is that there is a race condition here and the sequence process gets killed. This is because the sequencer's handle_reset() method stops all running sequences.

Hi! When I want to write/read transaction in test module i have an error

UVM_FATAL @ 0: reporter@@default_parent_seq [SEQNOTITM] attempting to start a sequence using start_item() from sequence 'default_parent_seq'. Use seq.start() instead.

when i change the
amiq_apb_master_simple_seq to amiq_apb_master_drv_item
also i change in bus2reg function
amiq_apb_mon_item transaction to amiq_apb_item transaction;

now reg test work fine

virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);
		amiq_apb_master_drv_item transaction; 
		transaction = amiq_apb_master_drv_item::type_id::create("transaction");

		transaction.address.rand_mode(0);
		transaction.data.rand_mode(0);
		transaction.rw.rand_mode(0);
		transaction.selected_slave.rand_mode(0);
		assert (transaction.randomize()) else 
		uvm_fatal("AMIQ_APB_NOSEQITEM_MSEQ_ERR", "The item could not be generated");

		transaction.address = rw.addr;
		transaction.data = rw.data;
		transaction.selected_slave = 0;
		if(rw.kind == UVM_WRITE) begin
			transaction.rw = WRITE;
		end
		else begin
			transaction.rw = READ;
		end
		return transaction;
	endfunction

	virtual function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op rw);
		amiq_apb_item transaction;
	  
		rw.status = UVM_NOT_OK;

		if($cast(transaction, bus_item)) begin
			if(transaction.rw == WRITE) begin
				rw.kind = UVM_WRITE;
			end
			else begin
				rw.kind = UVM_READ;
			end

			rw.addr = transaction.address;
			rw.data = transaction.data;
			rw.status = UVM_IS_OK;
		end
		else begin
			uvm_error(get_id(), $sformatf("casting did not worked - bus_item: %s", bus_item.convert2string()))
		end
	endfunction

by the way
https://github.com/amiq-consulting/amiq_apb/blob/master/examples/reg/tests/amiq_apb_ex_reg_test_random.sv#L54
when you use this kind of seq in reg test you don't use adapter.

		virtual task run_phase(input uvm_phase phase);
			amiq_apb_ex_reg_virtual_sequence_master_random master_seq;
	                uvm_status_e        uvm_status;
	                uvm_reg_data_t      data_read;
			phase.raise_objection(this, $sformatf("Start of test: %s", get_name()));

			reg_block = env.reg_block;
			reg_block.data[0].read(uvm_status,data_read);

It's not possible to configure an environment without any master or with a passive master. This would be useful when verifying an APB master (e.g. a bridge).

The code for wait_reset_end in the config class should be changed to:

virtual task wait_reset_end();
if(reset_active_level == 0) begin
@(posedge dut_vif.clk iff dut_vif.reset_n != reset_active_level);
end
endtask

This is because the protocol specifies behavior in terms of the first clock cycle after reset. This is also when a master should start driving its items, not immediately as the reset is de-asserted.