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ahb2

AMBA AHB 2.0 VIP in SystemVerilog UVM

amba_apb_sram

AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).

amiq_apb

SystemVerilog VIP for AMBA APB protocol

apb_spi_master

awesome-dv

Awesome ASIC design verification

gen_apb_file

kernel

These kernels can be used on Armbian and OpenWrt systems.

open-register-design-tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

open_regmodel

:hatched_chick:Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.

opentitan

OpenTitan: Open source silicon root of trust

panda

riffa

The RIFFA development repository

second_edition

Code for the second edition of Advanced UVM.

simple_reg_model

System verilog register model for uvm testbenches.

srm_sap

Simple as possible demo using simple_reg_model

tvip-axi

AMBA AXI VIP

uvm-apb_ral

This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.

uvm-generator

UVM Auto Generate ; Verify Project Build; Verilog Instance

uvm_testbench_gen

Novel GUI Based UVM Testbench Template Builder

v2ray

最好用的 V2Ray 一键安装脚本 & 管理脚本

withme-ios

WithMe App for iPhone.

xray

最好用的 Xray 一键安装脚本 & 管理脚本

yasky7.github.io

响应式的Jekyll主题

you7.github.io

test