alexforencich / verilog-cam Goto Github PK

You have the following link in your readme:
For more information and updates: http://alexforencich.com/wiki/en/verilog/cam/start

However, there is nothing there. Are there any instructions for how to run this?

RAM_DEPTH is automatically set to 2**ADDR_WIDTH inside the CAM, though there are applications where RAM_DEPTH (the number of entries in the CAM) is not necessarily a power of 2. For example a 96 entries CAM with ADDR_WIDTH = 7, RAM_DEPTH need not be 128, but RAM_DEPTH=96 will suffice. It will make the CAM implementation smaller and faster.

From what I could inspect in the code, it is quite trivial to add as a parameter.

Hi:
Sorry to bother you again.
This time i am using the cam module , but i found some of the ports are being unspecified, so i want to know is there any timing specifying of the ports of cam.v, for example what did the ports write_enable and write_delete mean?
Thanks a lot for your help.

Hello!

Hope you're doing well, and sorry to bother you. I am currently using your design for one my implementations. However, I require that the write operation last less than 4 cycles (2 if possible).
I was wondering if you could give me a pointer on how could I achieve this ?

Thanks!

Hi Alex,

I'm considering using this cam on vcu118 to replace the one provided by Xilinx. The reason is that I found xapp1151 doesn't work as it should on vcu118 (250MHz). It would be great if you can answer some of the questions I have:

1. Is this cam able to work on 250MHz on ultrascale+ FPGAs like vcu118?
2. Could the data width be extended? For example, we would like it to be extended to 201b (not aligned with 2^).
3. Is it possible to support ternary mode using this cam?

Happy new year and thanks in advance.

Regards,
Xiangrui