About axil-interconnect about verilog-axi

[omeag]

And, in this code below, I see when arvalid is received, s_axil_arready is set to 1. Did you verify whether the slave was idle during this process? What happens if the slave is not free?
if (read) begin
// reading
axil_addr_next = current_s_axil_araddr;
axil_prot_next = current_s_axil_arprot;
s_axil_arready_next[s_select] = 1'b1;

[alexforencich]

In AXI and AXI lite, if you start a write operation by setting awvalid high, you must complete it by providing the write data and setting wvalid high. If you didn't intend to perform a write operation, then don't set awvalid high in the first place..... If you don't follow the protocol, then you will likely get a hang and you'll have to reset the entire design.

For the second question, it doesn't matter if the slave is idle or not, the interconnect accepts the address, decodes it, and then presents it to the slave, then waits for the slave to accept it. The ready signal question is going to the upstream master that's issuing the request.

[shawn110285]

Just to make sure, Should I connect a ram (also from axi_ram.v in your repo) to the axi_interconnect's slave port or master port? My understanding is that I should connect axi_ram to the axi_interconnect's master interface, since the interconnect acts as the master and the ram acts as the slave? and the signals slave and master ports in the axi_connect should be identical? In the current implementation they are different, for example, the awregion, arregion presented in the master but not missed from the slave port.

[alexforencich]

Yes, that is correct - connect the RAM (which is an AXI slave) to a master interface on the interconnect. The awregion/arregion signals are used to address multiple regions within the same slave so that the slave doesn't need to do a second round of address decoding, it can simply use the region indication from the interconnect. Currently, I don't have any devices that take advantage of that feature, but it is part of the AXI spec.

[mrdiogodias]

Hello sir,
I'm also trying to use your axi lite interconnect but I'm having difficulties in how to use it. Do you have any example where you use it?

Thank you :)

[mrdiogodias]

Nvm, #16 answered my questions.
Thanks for your work