Axi DMA consistently returns DECERR about verilog-axi

[alexforencich]

Is this a spurious DECERR, or does this correspond to a DECERR on bresp? If the latter, you have the destination address wrong or something else in your AXI infrastructure is screwed up.

[EnricoGiordano1992]

I confirm that DECERR is on bresp.

Can you suggest to me how to check where could be the problem?
This is my Vivado design
design_1.pdf

[alexforencich]

Sorry, I'm not familiar with the IPI flow. At any rate, DECERR is generated by the interconnect when it cannot decode the address. So either you're providing the wrong address, or the interconnect addressing is not configured correctly.

[EnricoGiordano1992]

Good point. I have done another test, connecting the Axi DMA to an Axi BRAM Controller. In this configuration, it seems that everything is ok, so is missing "something" in the connection between the AXI in PL and the AXI HP0 in the PS. I will keep you posted 👌

[EnricoGiordano1992]

@alexforencich did you ever tried the Axi DMA connected to the PS on a custom design? If yes, can you give me any advice for the Vivado / bare metal solution?

[alexforencich]

Not that specific module, but I have used the AXI DMA IF module on a Zynq as part of Corundum and it worked fine. This was with Linux running on the PS, and it basically worked on the first try once I got petalinux to build.