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This project forked from spinalhdl/vexriscv

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A FPGA friendly 32 bit RISC-V CPU implementation

License: MIT License

Shell 0.10% C++ 5.42% Python 0.15% C 4.33% Java 0.02% Scala 30.40% Tcl 0.41% Verilog 0.32% Assembly 57.83% Makefile 1.04%

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