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Mips five stage pipeline CPU
License: MIT License
This project forked from ucasfl/mips_cpu
Mips five stage pipeline CPU
License: MIT License
#encoding:UTF-8 cpu.h: 模块之间的op每一位分别代表什么指令。 mycpu_top.v: 向上对接soc_lite_top.v,内部调用各流水级模块以及寄存器堆模块。 nextpc_gen.v: 生成pc的模块,生成的pc传入fetch流水级。 fetch_stage.v: 取指流水级,接受nextpc_gen传入的pc,将取回的inst传入下一级。 decode_stage.v: 解码流水级,接受取指传入的inst并进行解码,对于跳转指令在本流水级内决定是否要跳转,其余指令解码成接下来的流水级方便执行的指令码传入下一级。 execute_stage.v: 执行流水级,接受解码传入的指令码,并调用alu模块进行需要的计算,将计算结果传入下一级。 memoty_stage.v: 访存流水级,进行LW所需要的访问内存。 writeback_stage.v: 写回流水级,将之前算出或从内存中取出的值写入寄存器堆。 regfile_2r1w.v: CPU内的寄存器堆。 alu.v: CPU内的算术逻辑单元。 forward.v: 数据前递需要的模块,处理所有的数据前递,并判断是否需要进行阻塞。 md.v: 乘除法器模块,调用生成的IP或我们自己写的除法器进行乘除运算。 div.v: 除法器模块,进行有符号及无符号除法运算。 exception.v: 例外模块,实现例外的汇总与统一报出。 cpu_axi_interface.v: 接口转换桥,实现从sram like接口到axi接口的仲裁及转换。 sram2like.v: 接口转换桥,实现从sram接口到sram like接口的转换。 tlb.v: tlb模块,实现tlb的地址映射、tlb指令以及tlb例外功能。
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