14010007517 Goto Github PK

14010007517.github.io

2020nscscc

Chongqing University 2020 NSCSCC

3d_neurosim_v1.0

Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration

assembly-naivemips

Simple programs (NaiveBootloader, HWTest, etc.) written in MIPS assembly

behoo

bram

bram

ca_new_trends

some news or blogs for new computer architecture like risc-v, xPU, ASIC, etc....

cdma_training

cdma_training

christmassoc

Dual-core RISC-V SoC with JTAG, atomics, SDRAM

co_ext_lab-cqu

重庆大学计算机硬综拓展实验，对应在写的教材。

e203_hbirdv2

The Ultra-Low Power RISC-V Core

electron-ssr-backup

electron-ssr原作者删除了这个伟大的项目，故备份了下来，不继续开发,且用且珍惜

git-study

a doce of git study

h265-encoder-rtl

hd_img_resize

resize img using HD

irq_pspl

irq_pspl

jpeg-decoder

Verilog Code for a JPEG Decoder

jpeg_encoder

linux-kernel

Linux kernel source tree

loongsoncsprj2017

Computer System Project for Loongson FPGA Board in 2017

mangomips32

A softcore microprocessor of MIPS32 architecture.

microsoft-activation-scripts

A Windows and Office activator using HWID / KMS38 / Online KMS activation methods, with a focus on open-source code and fewer antivirus detections.

mips_cpu

Mips five stage pipeline CPU

mirror-swamp

MIRROR_SWAMP is a MIPS processor capable of booting linux, and it is specially optimized for DDR3 memory access pattern.

missing-semester-cn.github.io

the CS missing semester Chinese version

mqsim

MQSim is a fast and accurate simulator modeling the performance of modern multi-queue (MQ) SSDs as well as traditional SATA based SSDs. MQSim faithfully models new high-bandwidth protocol implementations, steady-state SSD conditions, and the full end-to-end latency of requests in modern SSDs. It is described in detail in the FAST 2018 paper by Arash Tavakkol et al., "MQSim: A Framework for Enabling Realistic Studies of Modern Multi-Queue SSD Devices" (https://people.inf.ethz.ch/omutlu/pub/MQSim-SSD-simulation-framework_fast18.pdf)

my_design

带有tlb的五级流水CPU

naivemips-hdl

Naïve MIPS32 SoC implementation

nontrivial-mips

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

nscscc2018

nscscc2018