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2020nscscc's Introduction

2020NSCSCC

PipelineMIPS

目标

设计并实现一个流水线版的MIPS处理器,力求:

  1. 模块清晰易懂,代码规范
  2. 有较为完善的Cache
  3. 主频达到100MHz
  4. 有TLB支持,便于之后运行操作系统

设计

  1. 指令集为MIPS32 Release1子集。初赛(57 条), 决赛(增加上学期跑PMON, linux时添加的指令)
  2. 采用流水线结构(5级或7级)
  3. Cache:一级cache,组相联结构,块大小为多字。
  4. Cache和TLB结合:虚拟索引,物理tag
  5. 分支预测模块

现有成果

  1. 通过初赛所有测试:功能测试,记忆游戏,性能测试,系统测试;上板通过;

  2. 频率 性能得分 IPC比值
    初赛提交版本 85MHz 48.130
    初赛后续优化版本 100MHz 55
    决赛提交版本(含TLB) 90MHz 28.156
  3. 启动并能够运行PMON,并成功运行移植的“猜数”小游戏。

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