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Delta-Sigma modulator (DSM) for fractional phase locked loop.

License: MIT License

Verilog 91.81% MATLAB 8.19%

delta-sigma-modulator's Introduction

Delta-Sigma-Modulator

Delta-Sigma modulator (DSM) for fractional phase locked loop.

File Structure

.
├── HK-MASH-DDSM  # HK-MASH or Traditional-MASH
│   ├── rtl       # verilog
│   └── tb        # testbench
├── SP-MASH-DDSM  # SP-MASH
│   ├── rtl
│   └── tb
├── PSD
│   └── PSD.m     # Calculate the power spectral density
├── LICENSE
└── README.md

Recommended parameter settings

Traditional MASH DSM

top: HK-MASH-DDSM/rtl/hk_mash111.v

parameter value
WIDTH 9
A_GAIN 0
OUT_REG 1

HK-MASH DSM

top: HK-MASH-DDSM/rtl/hk_mash111.v

parameter value
WIDTH 9
A_GAIN 2
OUT_REG 1

SP-MASH DSM

top: SP-MASH-DDSM/rtl/sp_mash111.v

parameter value
WIDTH 9
OUT_REG 1

Analysis

Traditional MASH DSM

Traditional-MASH_DSM

In HK-MASH-DDSM/rtl/hk_mash111.v, when parameter A_GAIN is set to 0, hk_mash111 works in traditional mode.

When input width(parameter WIDTH in hk_mash111) is set to 24bit(WIDTH = 24) and the input is 0.5(x_i = 2^23), the Power Spectral Density(PSD) of output is shown in the figure below.

hk_mash_24bit_i05_a0_psd

HK-MASH DSM

HK-EFM

In HK-MASH-DDSM/rtl/hk_mash111.v, when parameter A_GAIN is not equal to 0, hk_mash111 works in HK-MASH mode.

The relationship between coefficient a and parameter A_GAIN in hk_mash111 is shown in the following formula.

a = A_GAIN*2-1

Parameter detail:

parameter value
WIDTH 24
A_GAIN 2
OUT_REG 0

When input width(parameter WIDTH in hk_mash111) is set to 24bit(WIDTH = 24) and the input is 0.5(x_i = 2^23), the Power Spectral Density(PSD) of output is shown in the figure below.

hk_mash_24bit_i05_a3_psd

SP-MASH DSM

SP-EFM

SP-MASH

When every EFM's input width is set to the same width, this structure operates bad. The following figure is the PSD of output when input is 0.5 of 24bit:

sp_mash_24bit_i05_psd

So change the structure like this:

SP-MASH-599

The input width of the first EFM is set to 5bit, other EFM input width is 9bit. Shift e_1 to the left by 4bits as the input of the second stage EFM.

Parameter detail:

parameter value
WIDTH 9
OUT_REG 0

Power Spectral Density(PSD) of output is shown in the figure below.

sp_mash_5-9-9bit_i05_psd

Improve

When the DSM of the above three structures is mapped to the circuit, you will find that there is a long logic path collecting all the adders. This can limit the operating frequency of the circuit. A sample way to avoid this is adding registers to cutoff long logic path.

However, if we add one register between two adjacent EFM, it can strengthen the noise at certain frequencies.

PSD of HK-MASH when input is 0.5 of 24bit with one output register:

hk_mash_24bit_i05_a3_oreg_psd

PSD of SP-MASH when input is 0.5 with one output register:

sp_mash_5-9-9bit_i05_oreg_psd

In order to match the timming of output, we add three registers to the first EFM output, add two registers to second EFM output and add one register to the last EFM output.

HK-MASH DSM 1:

Parameter detail:

parameter value
WIDTH 24
A_GAIN 2
OUT_REG 1

PSD(input 0.5):

hk_mash_24bit_i05_a3_oreg_match_psd

HK-MASH DSM 2:

Parameter detail:

parameter value
WIDTH 9
A_GAIN 2
OUT_REG 1

PSD(input 0.5):

hk_mash_9bit_i05_a3_oreg_match_psd

SP-MASH DSM:

Parameter detail:

parameter value
WIDTH 9
OUT_REG 1

PSD(input 0.5):

sp_mash_5-9-9bit_i05_oreg_match_psd

delta-sigma-modulator's People

Contributors

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