a one-cycle CPU finished on ModelSim
Design Description:
1, the CPU support instructions:
a) addu, subu, ori, lw, sw, beq, lui.
b) addi, addiu, slt, j, jal, jr
c) addi temporarily don't handle overflow.
2, the CPU is one-cycle and programmed in Verilog
For more information, please opent the Experiment Report.